Puyang Zheng

Schomburg-A ***B, *** Circle Rd., Stony Brook, NY, US, 11790 949-***-**** adkgkd@r.postjobfree.com EDUCATION

Stony Brook University, the State University of New York (SBU) NY, US Ph.D. Student, Electrical Engineering; GPA: 3.83/4.0 University of California, Irvine (UCI) CA, US

M.S., Electrical Engineering; GPA: 3.53/4.0

Xi’an University of Posts & Telecommunications (XUPT) Xi’an, China B.E., Microelectronic Science and Engineering; GPA: 3.24/4.0; Ranking: 5/104 08/2019-Present

09/2017-03/2019

09/2013-07/2017

SKILLS

Design: Low-power, LDO, ADC, OTA, PLL, RF Front End

EDA Tools: Cadence, ADS, Multisim, ORCAD, Protel 99, Modelsim, Vivado, Coventorware

Programming: C++, Verilog HDL, SystemVerilog, Labview, Python, C, MATLAB WORK EXPERIENCES

Graduate Teaching Assistant - SBU Stony Brook, United States

Teaching Assistant for ESE123 Introduction to Electrical and Computer Engineering 09/2020-12/2020

Teaching Assistant for ESE382 Digital Design Using VHDL and PLDs 01/2020-05/2020

Teaching Assistant for ESE323 Modern Circuit Board Design and Prototyping 08/2019-12/2019 Graduate Student Researcher - UCI Irvine, United States

A 4-Channel Ultra-Low Power Bioelectric Signal Acquisition System for Neural Probes 01/2019-03/2019 Undergraduate Student Researcher - XUPT Xi’an, China

Characteristics of Drain-Modulated Generation Current in N-type MOSFET 09/2014-05/2015

Reliability of EL Semiconducting Thin Film Luminescent Materials 09/2013-06/2014 TRAINNING

The Light of Microelectronics 2018 Summer Camp Xi’an, China Professional Skills Training of Digital IC Verification 07/2018-08/2018

Completed the design verification of a Multi-Channel Data Formatter by SystemVerilog and UVM

Created the floorplan of a Dual-Tone Multi-Frequency design and completed route and signoff solution

Designed an audio equalizer by using Labview and Mydaq board

Completed a design of calculator Verilog HDL and finished the functional simulation PROJECTS

Stony Brook University, the State University of New York (SBU) Stony Brook, United States Design of 8-bit Pipelined ADC in 600nm CMOS Technology 01/2020-05/2020

Designed a folded-cascode OpAmp with 1x closed loop gain, 70dB DC gain, 3V output swing and 50ns settling time / 18.5dB SNDR and 7.21 ENOB for 100 KHz input singal frequency under 10Ms/s Design of 8-bit Carry Select Adder Using 45nm CMOS Technology 08/2019-12/2019

Realized 6 GHz working frequency in schematics simulation / Realized 1.6 GHz working frequency in post layout simulation / Lowered the total power consumption as 592.5672 μW / Area of the design is 739.32 μm2 / The design objective is about 3.65 1015 Hz/(W·m2) University of California, Irvine (UCI) Irvine, United States A 3-bit 20Gsamples/sec CMOS Flash ADC in 65nm CMOS Technology 04/2018-06/2018

Realized high precision of 0.26 LSB the worst INL and 0.069 LSB the worst DNL / Realized 18dB SNDR and 2.7 bits ENOB at 50 MHz / Realized 4.38 mW low power dissipation Two Stage Operational Amplifier Design in 45nm CMOS Technology 01/2018-03/2018

Designed a two stage OTA with 30dB gain and 6MHz 3dB bandwidth / Analyzed the transconductance and DC gain with Miller’s effect / Modified it with cascade structure and completed close loop analysis Design of MEMS Accelerometer in Coventorware 09/2017-12/2017

Designed accelerometers to detect 2 times of gravity acceleration / X or Y axis: designed the accelerometer of 10002μm2 area and 1.445 10-9 F/(m/s2) sensitivity / Z axis: designed the accelerometer of 5002μm2 area and 7.772 10-4F/(m/s2) of z axis accelerometer Xi’an University of Posts & Telecommunications (XUPT) Xi’an, China Design of Fractional-N Divider in GNSS Front End Frequency Synthesizer 02/2017-06/2017

Modeled MASH1-1-1 Δ-Σ modulator in ADS to obtain its power spectrum density, and analyzed its noise shaping ability / Described the circuits by Verilog HDL, and completed functional simulation / Operated Design Compiler to synthesize the circuits, Prime Time to analyze its static timing Fabrication Project 03/2017

Manufacture diodes on the wafer in cleanroom, and tested the resistance and I-V characterisitc of diodes RELEVANT COURSEWORKS

Analog IC Design, Digital IC Design, IC Verification, FPGA Design, Layout Design, Signal and System HONORS AND AWARDS

RA Studentship of ECE Department, Stony Brook University

TA Studentship of ECE Department, Stony Brook University

Excellent Graduated Student of Year 2017 XUPT

Excellent Graduation Design

Chancellor’s Scholarship of XUPT for two times (One among each 104 Major Students)

Merit Student of XUPT for three times

Third-class Scholarship of XUPT (Top 30% among 104 Major Students) 02/2021-present

08/2019-present

06/2017

06/2017

12/2015-12/2016

12/2014-12/2016

12/2014

Contact this candidate