Design Engineering
Resume:
NAME : HEMAPRASANTH U
DEGREE : Bachelor of Engineering
BRANCH : Electrical and Electronics Engineering (Sandwich) COLLEGE : PSG College of Technology, Coimbatore
Father’s Name Uthamaputhiran M
Gender Male
Date of Birth 10th November 1998
Languages English, Tamil
E-mail hemaprasanth.uthaman9
@gmail.com
Contact Number +91-948*******
ACADEMIC RECORD
Course Institution Board/University Completion By Marks BE
PSG College of
Technology
Anna University 2021 78.6*
XII
Sri Venkateswara
Matriculation Higher
Secondary School,
Vandavasi
Tamilnadu Board of
Higher Secondary
Education
2016 87.6
X
Sri Venkateswara
Matriculation Higher
Secondary School,
Vandavasi
Tamilnadu Board of
Secondary
Education
2014 86.66
* - Marks upto 7th semester
Semester I II III IV V VI VII
CGPA/10 7.4 7.37 7.56 7.72 7.81 7.84 7.86
AREA OF INTEREST
• Power Electronics • Machines
SKILL SET
Languages C, Verilog
Platforms Windows
Tools MATLAB,maxwell
INTERNSHIP DETAILS
Name of the Industry Duration Area of Exposure
Indian Space Research
Organization, Kerala.
12 weeks
Design of ASIC processor using
Verilog
Permanent Address
133A, Akilandeshwari St.,
Gajalakshmi Nagar,
Vandavasi,
Tiruvannamalai (Dt.) – 604408,
Tamilnadu.
TRAINING DETAILS
Name of the Industry Duration Area of Exposure
PSG Industrial Institute,
Coimbatore.
72 weeks
Manufacturing, Assembly and
Testing of Induction Motors and
Submersible Pumps
Tuticorin Thermal Power Station,
Tuticorin
1 Week
Study of Thermal Power
Generation Process,
Transmission and Distribution
PROJECT DETAILS
SIMULATION OF PMDC MOTOR:
Description: FEA is an advanced method of simulating an electro-mechanical system. The dimensions of a PMDC motor used in SEGWAY is obtained and it is simulated using Maxwell. It is then verified using testing of the motor. Design of Switched reluctance machine drive for light electric vehicle: Description: SRM ratings and battery is selected based on given mechanical performance. For the selected SRM, electric drive is designed. MOSFET selection, heatsink thermal resistance calculations are done. For the selected MOSFET, a gate driver is designed using IR2110 and simulated in LTspice. Controller is designed using PIC18F4550 and simulated in proteus. Eventually PCB layout of SRM drive is prepared using EasyEDA. HDL DESIGN OF ASIC PROCESSOR:
Description: This project involved hardware design of an Advanced Encryption Standard Algorithm using Verilog which uses 128 bit cipher key. The algorithm was implemented in pipelined and non-pipelined fashion. The design involves two units which runs parallely. The hardware was successfully synthesized and comparision is made between Pipelined and Non-Pipelined Implementation.
CO-CURRICULAR ACTIVITIES
• Second Runner-Up in MICROSOFT CODEFUNDO++ 2018 contest
• Mini Projects
1. Implementation of booth multiplication unit in MIPS 32 processor. 2. Design of counter to count no of products manufactured using 8051 microcontroller.
• Workshop
1. Quadcopter Workshop organized by Pragyan 2K17, NIT, Tiruchirappalli. 2. PLC and HMI Workshop organized by SRiSHTi 2K16
EXTRA-CURRICULAR ACTIVITIES
• Served as Executive for Youth Red Cross Society
HOBBIES
• Kabaddi • Badminton
DECLARATION
I, Hemaprasanth U, do hereby declare that the information given above is true to the best of my knowledge.
Place: vandavasi
(HEMAPRASANTH U)
U)
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