VIKAS KUMAR

MTech Microelectronics at IIIT-Allahabad

+91-785******* adkdtv@r.postjobfree.com

PROJECTS

Design and Implement, 32 Bit RISC processor using Verilog

• Implemented 32-bit RISC Architecture based processor with and without pipeline Architecture

• Implemented R-type, J-type, I-type Instruction set Architecture (ISA) Design fully Synthesized Asynchronous FIFO for (CDC) Clock Domain Crossing. also design Synchronous FIFO using Verilog

• Asynchronous FIFO designed based on dual N-bit, N-1 Gray counter-based Architecture, Two _op synchronizer, Flag: Empty, Full Flag

• synchronous FIFO using Queue data structure, with the help of binary pointer.

Design Fast, Efficient Integrated Round Robin Arbiter

• Design and Implemented on Xilinx spartan 3 FPGA Board. It can handle 4 request line.

• Priority is deciding based on Round Robin Scheduling Algorithm. Tool- Xilinx Vivado, FPGA board

Design of a two-stage OP-AMP using UMC 180nm Technology

• Two stages OP-AMP with Gain=62dB, GBW=30 MHz, PM=60, Slew rate= 20v/us power dissipation 0.3mW. Designed and simulated in Cadence Virtuoso using UMC 180nm technology.

Design and Simulate of Bandgap reference Circuit (BGR) using UMC 180nm Technology

• Design Current mirror-based Bandgap Voltage reference circuit with start-up circuit (Temp range -20 C to 140 C, Vout= 1.154v, well curve voltage = 0.015v, Vdd =1.8v) with Cadence Virtuoso, LT-Spice Also design 1v Sub BGR circuit

Design Low Voltage, High PSRR, Low Dropout Voltage Regulator

(LDO)

• LDO work on (0.85v < Vin < 2.1v, Vout= 0.800v, PSRR@ 100KHz= 60dB, Cload

=10u with Rser=1ohm, Max load current 50ma, load regulation =0.083%, Line regulation=1.2%, Current Efficiency= 98.5%)

WORK EXPERIENCE

Intern in KeenHeads Technologies Pvt, Delhi (June 20 – Nov 20) In these 6 months, I work on Analog Design & Analog Layout Design in 45nm, 90nm, 180nm. this Internship, I worked on LDO, OP-Amp, BGR layout design using the Cadence Virtuoso tool.

Internship at IISc Bangalore DESE Department. Design a project on an embedded system. (June 18 – July 18)

Design Automatic door Security System Using ARM-Based TI Launchpad

CERTIFICATIONS

VSD – Physical Design Flow,

VSD – Signal Integrity

Learn the concept of Physical design flow such as Floorplan, Placement and Routing, Static timing Analysis, Parasitic Extraction, Cross Talk, Power Noise vikas-kumar-ba8330112 Delhi, India

SKILLS

Top Skills RTL Coding, Digital Design, Analog

Layout, and Analog Design

Tools and Tach. Xilinx Vivado, Questa & ModelSim,

Cadence Virtuoso, Calibre & HSpice,

Synopsys DC, LT-Spice

Prog. & Protocol Verilog, C/C++, MATLAB, TCL & Perl Scripting, Unix Shell, SPI Interface, I2C

Skills ASIC Design Flow, Analog Design Flow,

Logic Synthesis, Physical Design Flow

Static Time Analysis, STD. Cell Layout

Design, PCB Design (Easy EDA)

EDUCATION

MTech Microelectronics

IIIT, Allahabad

August 19 – June 21 CGPA- 8.0

Courses are taken: Intro. of Microelectronics, Digital VLSI Design, Programming for Eng. Application, Analog VLSI Design, Embedded Systems, Testing, and Verification, Hardware Design Methodologies, VLSI IC Technology, Mix IC Design, MEMS.

MSc Electronics

University of Delhi, Delhi

July 17 – June 19 74.50 %

Courses are taken: VLSI Circuit Design and Device Modelling, High-level Computer Language and operating system, Semiconductor Devices and Material, DSP, IC Technology, Computation Technique, Eng. Math, Analog and Digital, Circuit design and simulation, Microprocessor. Project- Antenna Design, Simulation, and Fabrication of Microstrip Antenna for Wireless WLAN Application

BSc. (Hons) Electronics

Hansraj College, University of Delhi

July 14 – June 17 65.11 %

Intermediate

Board of Intermediate Education Uttar Pradesh

July 13 – May 14 84.80 %

Matriculation

Board of Intermediate Education Uttar Pradesh

July 11 – June 12 84.80 %

Contact this candidate