IC CAD or Layout

BRYAN TRUONG

**** ****** **..

El Cajon, CA *****

Cell: 408-***-****

Email: *********@*****.***

OBJECTIVE Seeking a challenging position in CAD or IC Layout.. EDUCATION Bachelor of Science in Electrical Engineering. Kansas State University, Manhattan, Kansas 66502

Relevant Courses:

● Integrated Circuit Engineering ● Electronics Instrumentation

● Design of Communication Circuits ● Electromagnetic Theory

● Communication Electronics ● Power Electronics

● Digital Communication Systems ● Control System Designs Design Projects/Experiments:

● Presented a paper on optical fiber in commercial and military communication systems.

● Designed a temperature controlling circuit to measure the characteristics of the LM741 amplifier and performed many power-electronics experiments as well.

● Designed and built a high-gain circuit to measure Johnson’s noise.

● Designed, implemented and tested RF mixer, IF amplifier and Phase-Locked Loop circuits for FM radio system.

● Worked on a designed project of sending video/audio from Mars observer.

● Fabricated the MOS devices on a silicon wafer.

● Presented the paper on synthetic diamond film used in microchip technology. Computer/Skills:

● Tools: Cadence, Avanti and Viewlogic. Programming: Dracula, Diva, Calibre, Hercules, C, Fortran and Basic. Dbases: IV, First Choice & Approach. Spreadsheets: Excel 5.0, Quattro Pro & Lotus 1-2-3. Word Processing: MS-Word, Word Perfect & AmiPro. Operating Systems: Unix and MsDos.

● Electronic Simulation/Analysis: Hspice, Pspice, MetaWaves, Touchstone, MicroCap II, Network/Spectrum Analyzers and Micrologic.

EMPLOYMENT

CAD/Verification Engineer - Consultant

Linear MicroSystems, Inc., 14 Goodyear, Irvine, CA(Present)

● Review and simplify foundry specifications.

● Implement test cases to evaluate the new released Process Design Kit.

● Schematic capture and IC layout in Cadence environment. CAD Engineer:

Analog Devices, Inc.,3550 North First St, San Jose, CA(02/08-2/18)

● Layout and backend verification support for 28nm process.

● Modify Calibre/Hercules/Dracula DRC and LVS to accommodate design requirements.

● Develop the new Calibre code to check dangling nets and floating metals for all existing ADI internal PDKs.

● Support backend verifications in Hercules, Calibre and Dracula.

● Responsible for any incoming CADBUGs from the local and remote sites.

● Manage SOS projects by using ClioSoft.

● Implement new pcells for ADI internal PDKs.

● Implement skill code to extract schematic device count.

● Responsible for the final layout review and signoff before taping out from San Jose site.

● Interact with the Verification Standard, Layout Productivity and Cadence Working Groups.

● Train designers to use new features after switching from IC5.1 to IC6.1.

● Convert and verify numerous designs from IC5.1 to IC6.1.

● Document new Cadence features and post on the internal Twiki webpage. CAD Engineer:

Exar/Sipex, Corporation, 48720 Kato Rd., Fremont, CA(01/01-2/08)

● Responsible for supporting, developing, and migration of physical design rule checks for various fabrication processes such as Jazz Semiconductor, UMC, ASMC, CMD, Sipex, PolarFab and Episil. Responsibilities are listed below:

● Develop Caibre DRC deck for 0.50um and 0.25um Bipolar Processes.

● Develop Diva EXT, LPE, and LVS for 1.2u CMOS and 0.8u Bipolar processes.

● Review and evaluate foundry specifications.

● Develop and test Diva DRC and Dracula LVS verification decks for 1.2um BiCMOS process.

● Develop and test Diva DRC decks for 0.8um and 2.0um BiCMOS processes.

● Develop and test a genetic 0.5um-Diva DRC deck for three different foundries.

● Develop and test Diva DRC deck for 3.0um process.

● Evaluate and test Cadence PDKs and Diva LVS/LPE decks for 0.8um and 2.0um processes.

● Cadence setup and design verifications/layout support.

● Modify pcells to meet the process design needs.

● Training: VCR, VXL, and Diva Verifications.

CAD Engineer:

Intel Corporation, 201 Mission St, San Francisco, CA(09/99-01/01)

● Modified Hercules DRC and LVS runsets to satisfy wireless group design requirements.

● Interfaced with CAD group in Sacramento before any tape-out from San Francisco.

● Pre/Post-archive verifications of the chip level.

● Archived and documented all the tape-out products.

● Installed Cadence licenses and backend support.

IC-CAD Engineer:

Glenayre, Wireless Access Group, 2101 Tasman Dr., Santa Clara, CA(03/99-09/99)

● License evaluation, recommendation and $1.17M purchasing.

● Maintained, updated, and re-configured Cadence licenses.

● Organized tools and directories and circuit documentation.

● Performed Diva DRC, LPE and LVS interactive verifications.

● Interfaced with foundry to resolve any discrepancy before tape out.

● Solaris System Administration I Certification.

● Resolved Unix system problems either personally or through consultant.

● Set up Unix accounts and maintained backups.

● Evaluated hardware and purchasing.

CAD Layout Engineer II:

Exar, Corporation, 48720 Kato Rd., Fremont, CA(06/96-03/99)

● Developed 0.6um-standard pad library into a superset and can be quickly implemented for all the design needs.

● Developed 0.6um-SRAM layout and schematic entry by using Cadence composer to ensure that meet all the physical and electrical specifications.

● Has shrunk seven products from 1.2um to 0.6um and 0.8um for cost reduction.

● Verified DRC and ERC prior to the tape-out. Supported pad level LVS debugging.

● Developed graphical 0.8um BiCMOS design rules and put them on the internal web browser by using HTML.

● Completed 0.6um, 0.8um and 1.6um layout designs for scribe-line test patterns and 1.6um process control monitor.

● Simulated ESD structures of 0.6um technology.

● Characterized 0.6um test patterns for modeling.

● Familiarized and learned DRC, ERC and LVS Dracula programming. Simulated ESD structures of 0.6um technology.

● Debugged and verified DRC, ERC and LVS for design supporting.

● Supported 0.6um-standard pad library and mask tooling cells.

● Had been recognized three times for the successful completed projects.

● Had been promoted for CAD Layout Engineer I to II after employed at Exar for less than 1.5 year.

Electronic Engineer:

Western Electronic Components, Corp., Camarillo, CA(09/93-06/96)

● R&D electrical material to formulate Positive Temperature Coefficient(PTC) and Negative Temperature Coefficient(NTC) thermistors of pre-specified properties.

● Designed, implemented, tested and evaluated the prototype of newly developed PTC and NTC thermistors to ensure satisfaction of all parameters required by customers.

● Established databases to expedite engineering and production processes.

● Supported management level to document, correct and improve company operation in order to qualify for ISO9001 standard.

● Technically resolved all production or scheduling difficulties base on engineering judgment.

● Investigated returned orders and documents to improve product quality. Grader/Help Section:

Department of Mathematics, Kansas State University(01/92-09/93)

● Graded mathematic home-works, quizzes and assisted students to solve problems. LEADERSHIP

& ACTIVITIES

● Member of NASA Advanced Design Team at Kansas State University(1992)

● Member of United States Achievement Academy, USAA(1992)

● Chairman of Asian Student Association at KSU(1990-1993)

● Member of Mathematics Club(1991)

REFERENCES

● Available upon request

● U.S Citizen and willing to travel/relocate.

Contact this candidate