Design and verification, ASIC design

SANTHOSH REDDY KOMATIREDDY

*************.***********@*****.*** 813-***-**** LinkedIn Github

EDUCATION

University of South Florida Tampa, FL

Master of Science in Electrical Engineering Aug 2018-May 2020 Coursework: Intro to VHDL and System Verilog, Integrated Circuit Technology, Integrated Systems Technology, MEMS, Chem Bio Sensors, System on Chip, Wireless Circuits/Systems Laboratory, Computer Architecture. Jawaharlal Nehru Technological University Hyderabad, India. Bachelor of Technology in Electronics and Communications Engineering Aug 2014-May 2018 TECHNICAL SKILLS

• EDA Tools: Siemens EDA - Questasim, Cadence-Virtuoso, Xilinx-Vivado, MATLAB, ModelSim, NCsim, Quartus Prime, Hspice, Keysight ADS, ComSol.

• Verification Methodologies: Constraint Random Coverage Driven Verification, Assertion Based Verification – SVA, Static Time Analysis.

• TB Methodology: UVM. BUS PROTOCOLS: AMBA AHB, APB, AXI.

• Programming/Scripting languages: C, C++, Perl, System Verilog, VHDL, Verilog, Assembly level language.

• Operating systems: Linux, Windows.

ACADEMIC PROJECTS

Design and Verification of AHB-APB Bridge IP Core.(SV, UVM) Maven Silicon June 2020 – Feb 2021

• Designed a class-based verification environment in UVM and defined the verification plan.

• Verified the RTL module with UVM Test Bench with different test scenarios like single READ, WRITE & Burst READ, WRITE with different burst lengths.

• Generated functional and code coverage for the RTL verification sign-off. DESIGN AND VERIFICATION OF DUAL PORT RAM. (SYSTEM VERILOG), USF

• Designed a class-based verification environment using System Verilog for test bench components such as generator, write BFM, write monitor, read BFM, read monitor, interface, reference model, scoreboard and testcases. Stimulus was driven by the driver to DUT.

• Implemented reference model in scoreboard and compared actual data with expected data in scoreboard, Generated functional and code coverage for the RTL verification sign-off. DIGITAL ALARM CLOCK DISPLAYS TIME IN LCD FORMAT IN A 24HR FORMAT USING VERILOG.

(EDA Tools: Modelsim, Quartus-prime)

• Developed an RTL code for each sub-blocks used in the block level architecture of the Alarm clock and verified each sub-block using task-based Verilog Testbench.

• Finally verified the top-level RTL using Verilog Testbench and generated code coverage for the RTL design sign- off.

DESIGN AND IMPLEMENTATION OF 16-BIT CARRY LOOK AHEAD ADDER(Tools: Cadence, NC-Sim simulator)

• Developed an RTL design and testbench for 16-bit CLA using behavioral and structural model using the cells described in TSMC 0.18µm standard cell library data book.

• Identified different delays occurring in the circuit using Cadence and determined the Behavioral model to be better than Structural model but structural model is used extensively. CERTIFICATION AND PROFESSIONAL TRAINING

• Completed online Professional training in Advanced VLSI Design and Verification at Maven Silicon from June 2020- Feb 2021.

• Online certification from Udemy in :SoC verification using System Verilog and UVM.

• Online certification from Coursera: Computer Architecture.

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