Engineering Design

Mukesh Kumar

Phone: 869-***-****, 706-***-**** Email: ***************@*****.*** PROFESSIONAL

SUMMARY

SKILLS

WORK HISTORY

The meticulous and analytical researcher with five years of educational and hands-on experience in VLSI low power design. Adaptive team player with in-depth knowledge of data collection and problem-solving. A highly motivated individual committed to hard work and intensive analysis. Flexible and polished senior Research associate promoting well-developed skills in the Cadence EDA tool and H-spice simulation tool.

• Cadence EDA tool

• Cogenda TCAD

• H-Spice simulation tool

• Tanner tool

• Experiment design

Published / to be published Research papers listed

• “Analysis of Ultra-low Energy and Reliable 10T SRAM Cell at Nano Technology” under review in Microelectronics journal (SCI Indexed Elsevier publication Journal).

• “Design and Analysis of CNTFET Based 10T SRAM for high performance at the nanoscale” Published in International Journal of Circuit Theory and Applications, 2019 (SCI Indexed Wiley publication Journal, IF= . ).

• “Consequences of body biasing technique on SRAM memory cell,” published in International Journal of Innovative Technology and Exploring Engineering (SCOPUS indexed), 2019.

• Mukesh Kumar, Manjesh Kumar, “A Survey on Various Approaches of Automatic Optical Inspection for PCB Defect Detection,” International Journal of Computer Sciences and Engineering, Vol.7, Issue.6, pp.837-841, 2019 (UGC APPROVED JOURNAL).

• “Analysis of Body bias impact on the performance parameters of CMOS Inverter” presented in the National conference held at NITTTR Chandigarh (SLIETCON-2019).

• “Low Power 3-Bit Flash ADC Design with Leakage Power Reduction at 45 nm Technology” IEEE International Conference on Information Science and Technology (ICIST 2018) in Spain during June 30-July 6, 2018 (SCOPUS indexed).

• “Comparative Analysis of Standard 9T SRAM with the Proposed Low-Power 9T SRAM” Springer International conference presented at Jaypee university Noida, published as a chapter in a book titled Advances in Signal Processing and Communication, Lecture Notes in Electrical Engineering https://doi.org/10.1007/978-***-**-****-3_52, 2018 (SCOPUS indexed).

• “Performance of 3-phase 4-wire distribution system with DSTATCOM and T-transformer for zero voltage regulation.” In 2016 International Conference on Computing, Communication and Automation (ICCCA), pp. 930-933. IEEE, 2016 (SCOPUS indexed).

• “Analysis of CMOS based NAND and NOR Gates at 45 nm Technology” International Journal of Electronics, Electrical and Computational System IJEECS ISSN 2348-117X Volume 6, Issue 4, April 2017.

• “Performance evaluation of 6T, 7T & 8T SRAM at 180 nm technology”, 8th International Conference on Computing, Communications and Networking Technologies, ICCCNT, 2017 organized at IIT Delhi (pp. 1–6). DOI: 10.1109/ICCCNT.2017.8204092 (SCOPUS indexed).

• “A Novel Approach of standard database generation for defect detection in Bare PCB” has been presented in International conference on computing, communication, and automation organized by IEEE in May 2015 (SCOPUS indexed).

• “PCB Image Enhancement using Machine Vision for effective defect detection” has published in the International Journal of Advanced Engineering Research and Science (IJAERS) in August 2014.

Workshop/Short term course attended

• Successfully completed the course on “LaTeX for Students, Engineers and, Scientists” organized by IIT Bombay, an online learning initiative of Indian Institute of Technology Bombay from 15 July to 15 December 2020.

• Participated in the five days online workshop on “Emerging CMOS Technologies and Beyond: Trends and Challenges” held at MNIT Jaipur during November 26-30, 2020.

• Participated in the “Skill Development Workshop for Verilog/System Verilog” held at MNIT Jaipur during 15th to 23rd October 2020 and 1st to 11th November 2020.

• Participated in the IEEE Electron Devices Society DL Mini Colloquium (Virtual) on “Emerging Nano Devices and Circuits – The Roadmap Ahead" organized Jointly by Department of Electronic Science, University of Delhi South Campus and IEEE Electron Devices Society Delhi Chapter, during October 05-09, 2020.

• Participated in the five days online workshop on “Recent Trends in VLSI Devices/Circuits and Applications” held at MNIT Jaipur during October 1-5, 2020.

• Participated in three days FDP on “Emerging trends of Organic LED” organized by SKIT, Jaipur, ECE department during July 27-29, 2020.

• Participated in one-week FDP on “Pedagogy of scientific writing, reporting and scholarly networks” organized by Feroz Gandhi institute of engineering and technology, Raebareli during June 19-23, 2020.

• Participated in “E-Shodh Sindhu Clarivate Web of Science Certification series” with 5 Sessions during May 14-28, 2020.

• Participated in a two-week workshop on “Python Programming” organized by SSDC, SLIET, Longowal during February 09-22, 2020.

• Participated in five days short term course on “Nano-electronics & VLSI: Devices, Circuits, and Systems” organized by ECE department, NIT Uttarakhand in collaboration with SLIET, Longowal during November 04-08, 2019.

• Participated in one-week Short term training program on “Recent Trends in Electronics and Communication Engineering” organized by ECE department SLIET, Longowal from September 24-28, 2018.

• Participated in one-week Short term training program on “Modelling and Simulation using MATLAB” organized by Electrical and Instrumentation department SLIET, Longowal from May 21-25, 2018.

• Participated in three days workshop on “Analog CMOS Integrated Circuit Design” organized by ECE department SLIET, Longowal from April 14-16, 2018.

• Participated in Faculty development program on “VLSI Devices and Technology” conducted by E&ICT Academy at IIT Roorkee from October 3-8, 2017

• Participated in two days TEQIP-II Sponsered workshop on “MEMs Systems and Design” organized by ECE department SLIET, Longowal from October 24-25, 2016.

• Participated in one-week Short term training program on “Frontiers in Electronics and Communication Engineering” organized by ECE department SLIET, Longowal from September 19-23, 2016.

• Participated in three days workshop on “Simulation and Modelling, organized by the Computer Science and Engineering department,” SLIET, Longowal from September 8-10, 2016.

• Participated in workshop on VLSI Design flow using Cadence EDA Tool organized by ECE department, SKIT, Jaipur from May 25-26, 2016.

Training /

Projects

undertaken

during B.Tech

EDUCATION

CERTIFICATION

EXPERIENCE

REFERENCES

• Participated in the Short term training program on “Renewable energy applications: Practices and Challenges” at SLIET, Longowal from December 21-25, 2015.

• Participated in one week Short term course on “Computer vision and pattern recognition” organized by the Information Technology department, NIT Durgapur from June 16-20, 2014.

• Participated in National workshop on “Biometrics and privacy protection” organized by the Computer Engineering department, MNIT Jaipur from December 23-25, 2013.

• Participated in two-week winter school on “Future trends of broadband wireless communications and networking” organized by ECE department, SLIET, Longowal from December 9-20, 2013.

• Accomplished 4 weeks training on “Automatic Car washing using Programmable Logic Controller (PLC)” at Webel Automation and Convergence Academy, Kolkata from 02.01.10 to 31.01.10.

• Accomplished 4 weeks training on “Vocational training in Mobile Switching Centre (MSC)” at Bharat Sanchar Nigam Limited, Patna from 28.06.10 to 09.08.10

• Accomplished final year project on “Microcontroller based automatic temperature controller.” PhD (VLSI technology and design) (Thesis Submitted), 07/15 to 02/21 Dissertation title: Radiation hardened SRAM memory design Sant Longowal Institute of Engineering Technology, Longowal, Sangrur, Punjab (CFTI) M.Tech (ECE), (Marks percentage obtained 71.28 % ), 09/2014 Dissertation title: Automatic defect detection in PCB using Machine vision Sant Longowal Institute of Engineering Technology, Longowal, Sangrur, Punjab (CFTI) B.Tech (ECE), (Marks percentage obtained 76.40 % ), 07/2011 Techno India College of Technology, WBUT, Kolkata

Intermediate, (Marks percentage obtained 68.44 % ), 07/2001 G. D. College, Begusarai, Bihar

Matriculation, (Marks percentage obtained 65.14 % ), 06/1999 B. S. S. Inter-Collegiate School, Begusarai, Bihar

• Qualified GATE Exam two times in 2019 and 2011 ( grab scholarship during M.Tech).

• UGC NET also qualified for two times in December 2013 and June 2014.

• Paper reviewer in peer-reviewed SCI/ SCIE journals like International Journal of Circuit Theory

& Applications, and Semiconductor Science & Technology I had joined PhD on 28th July 2015 and worked on the Cadence EDA tool to learn schematic as well as the layout of the design. I worked here as a JRF during this period from 28/07/15 to 27/07/18. I had worked as an SRF from 28/07/18 to 27/07/20 during my PhD and learned on the Cadence EDA tool as well as the HSPICE tool to solve problems and publish papers in the peer-reviewed journal and international conferences.

Senior Lecturer (02/08/2014 – 27/07/2015)

Jaipur Engineering College and Research Center, Jaipur, Rajasthan Assistant Professor (26/08/2011 ̶ 25/07/2012)

SLBS Engineering College, Jodhpur, Rajasthan

1. Dr. Anupma Marwaha 2. Dr. J. S. Ubhi

Professor Professor

ECE Department ECE Department

SLIET, Longowal (Punjab) SLIET, Longowal (Punjab)

DECLARATION

I hereby declare that all the information furnished above is true to the best of my knowledge. Date: Signature

Place: (MUKESH KUMAR)

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