* ** *

Tolga Yalcin

**** * **** **, *********, *6001 AZ, USA

Phone: 928 – 699 0778

Email: adjxx7@r.postjobfree.com

Skills

- 20+ years digital circuit design: Cryptographic modules, forward-error correction modules, digital filters, rake receivers, application-specific fixed and floating-point microcontrollers, application-specific datapaths (mostly for digital transceiver designs) in both Verilog/VHDL, full-custom design of systolic arrays.

- 10+ years embedded security: Design, implementation of symmetric and asymmetric cryptographic primitives for FPGA and ASIC platforms including linear, differential and biclique cryptanalysis, side- channel attacks and countermeasures, design of parallel computing platforms for efficient cryptanalysis.

- 5+ years analog/mixed-signal CMOS IC design: Current mode D/A converter design, audio amplifier design (single-ended and differential), continuous-time and switched capacitor filters, full-custom digital standard cell library development.

- 2+ years RF IC design: VCOs, LNAs, mixers

- Experience with Synopsys DC, Synplicity, Xilinx Vivado/IDE, Verilog-XL, VCS, Modelsim, Cadence Encounter/Analog Artist/Spectre RF, Matlab, Advance Design Systems (ADS), C, Perl, Unix shell Work Experience

Northern Arizona University, Flagstaff, AZ

Assistant Research Professor

2018 – present

- Teaching classes in Error Control Coding, Fundamentals of Computer Engineering, Design for Security

- Leading cryptographic and DSP hardware research activities:

- Design of RF interference mitigating (RFIM) receiver backend for NASA,

- Design of a secure RISC-V processor core for AFRL,

- Design of post-quantum cryptographic (PQC) modules for AFRL. NXP Labs UK, Glasgow, United Kingdom

Hardware Security Engineer

2016 – 2018

- Design and FPGA implementation of crypto and control units for hardware-assisted countermeasure for software control flow integrity

- Design and implementation of an SCA and FA resistant secure DES core TY Consulting, Izmir, Turkey

Hardware Design Consultant

2006 – 2016

- ASELSAN Inc, Ankara, Turkey: Side-channel attacks on block ciphers, development of countermeasures, architecture development, RTL implementation (VHDL) and verification (VHDL and bit-exact Matlab) of cryptographic modules (AES, SHA, DES, RSA, ECC, IPSec) for industry standard and in-house algorithms, design and implementation of video IPs (format converter, resizer, deinterlacer, image enhancement filters) for a custom video processing unit,

- Maxim Semiconductor, San Jose, CA: Design and implementation of interface modules for ultrasound processing ICs,

- Microsemi Corporation, Aliso Viejo, CA: Design and implementation of a SCA resistant ECC core,

- Percello Ltd, Raanana, Israel (now Broadcom): Architecture development, RTL implementation and verification of an IPsec processor and cryptographic coprocessors (AES, 3DES, SHA, RSA), software implementation of the full IPv4 protocol stack,

2 of 3

- Synopsys, Mt View, CA: Design of a Reconfigurable Reed-Solomon Encoder/Decoder IP for Synplify DSP IP library,

- ArrayComm, San Jose, CA: Design and implementation of a custom RISC for WiMax applications Ruhr University, Bochum, Germany

Postdoctoral Researcher

2011 – 2013

- Teaching classes in Advanced Digital System Design,

- Conducting cryptographic hardware research activities:

- Design, implementation and classification of s-boxes for optimal power and area,

- Design and implementation of hardware for high-performance linear, differential & biclique cryptanalysis,

- Design of a low-latency block cipher for pervasive computing applications (PRINCE),

- Design of a block cipher for optimized for IoT applications on 8-bit microcontrollers (PRIDE),

- Lightweight implementation of symmetric/asymmetric cipher cores,

- Design and implementation of hardware for attack against Truecrypt encrypted files on Copacabana.

University of Applied Sciences and Arts, Lucerne, Switzerland Graduate Research Assistant

2003 – 2006

- Graduate Study towards Ph.D. degree at the Swiss Federal Institute of Technology (EPFL):

- Integrated microwave electronics for Electron Spin Resonance (Ph.D. Thesis),

- Design, implementation and tests of building blocks for the on-chip ESR spectrometer such as sensor microcoils, VCOs, LNAs, mixers and IF amplifiers. ArrayComm LLC, San Jose, CA

Sr. ASIC Design Engineer

2001 – 2003

- Design and implementation of i-Burst air interface security module: Matlab realization, RTL implementation of various stream/block ciphers (RC4, DES, AES, TEA) and a custom co-processor

(capable of implementing finite field arithmetic operations up to GF(2^233)).

- Design of IntelliCell ASICs for smart antenna handsets: Matlab modelling of smart antenna functions for hardware implementation, implementation, simulation and RTL realization of functional blocks for smart antenna signal processing (digital AGC, CDMA incremental searcher, PN code generator, matrix calculation blocks and associated arithmetic units, custom 20-bit floating point DSP and UART). Philips Semiconductors, Zurich, Switzerland

Sr. ASIC Design Engineer

2000 – 2001

- Hardware verification of GSM digital baseband processors on a Quickturn Mercury+ hardware emulator, includes setting up a Quickturn Mercury+ based verification environment.

- Design of the audio path for the next generation GSM digital baseband processor: Matlab/C modelling and simulations of a continuous-time SIGMA-DELTA A/D CONVERTER, design of a decimation circuit, implementation of digital IIR bandpass filters.

TUBITAK BILTEN, Ankara, Turkey

Lead IC Design Engineer

1991 – 1999

- Full-custom design of a two stage (6-bits/stage) multiplying DAC with current output,

- Design of an audio processing IC: Matlab modelling of a discrete-time sigma-delta A/D converter, Matlab and RTL design and verification of the decimation circuit and voiceband filters, full-custom design of switched capacitor filters for application specific data processing, layout generation of the digital section of the IC using Cell Ensemble, floorplaning and full-custom layout generation of the whole IC, physical verification and post layout simulations, 3 of 3

- Design of a 16x16 hierarchical PN-code digital matched filter (DMF) for instantaneous code acquisition in 3G WCDMA systems: Matlab modelling, RTL coding and verification of the DMF,

- Design of a control-aided FPGA for a spread spectrum communication system: RTL and Xilinx FPGA realization and verification of timing / control blocks and PN-code generator,

- Digital 3x8 PBX (Private Branch Exchange) IC design: digital standard cell library creation, frontend design of a DTMF tone generation block, multiplier-free bit-serial digital filters for DTMF side-tone suppression and voice band signal processing (Matlab modelling and simulation included), floorplaning, layout generation and physical verification of the whole IC. Education

Ph.D. in Microelectronic and Microsystems

Swiss Federal Institute of Technology Lausanne (EPFL), Lausanne, Switzerland

- Dissertation Title: Microwave integrated electronics for ESR spectroscopy 2004 – 2007

M.Sc. in Electrical and Electronic Engineering

Middle East Technical University (METU), Ankara, Turkey 1992 – 1994

B.Sc. in Electrical and Electronic Engineering

Middle East Technical University (METU), Ankara, Turkey 1988 – 1992

Training

- Advanced Engineering Course on RFIC Design, EPFL, Switzerland, October 2005

- Advanced Engineering Course on PLLs, Clock & Data Recovery, EPFL, Switzerland, June 2004

- Quickturn MercuryPlus System Advanced Training, Zurich, Switzerland, Oct. 2000

- Ambit BuildGates On-site Training, Zurich, Switzerland, Feb. 2000

- Advanced Engineering Course on CMOS/BiCMOS Design (Digital), EPFL, Switzerland, Aug.1998

- Advanced Engr. Course on CMOS/BiCMOS Design (Mixed-mode), EPFL, Switzerland, Aug. 1997 Selected Publications

- Magnetic resonance spectrometer suitable for integration on a single chip: International Patent Nr. WO/2007/128140

- E. B. Kavun, H. Mihajloska, T. Yalcin, “A Survey on Authenticated Encryption – ASIC Designer’s Perspective”, ACM Computing Surveys, 50 (6), Part B, pp. 592-598, 2017

- T. Yalcin, “Compact ECDSA engine for IoT applications”, Electronics Letters, 52 (15), pp. 1310-1312, 2016

- M.R. Albrecht, B. Driessen, E.B. Kavun, G. Leander, C. Paar, T. Yalcin, “Block Ciphers – Focus On The Linear Layer (feat. PRIDE)”, CRYPTO 2014, Santa Clara, California, USA, 17-21 August 2014

- S. Engels, E.B. Kavun, H. Mihajloska, C. Paar, T. Yalcin, “A Non-Linear/Linear Instruction Set Extension for Lightweight Ciphers”, ARITH 21, Austin, TX, 7-11 Apr 2013

- J. Borghoff, A. Canteaut, T. Güneysu, E. B. Kavun, M. Knezevic, L. R. Knudsen, G. Leander, V. Nikov, C. Paar, C. Rechberger, P. Rombouts, S. S. Thomsen, T. Yalcin, “PRINCE – A Low-Latency Block Cipher for Pervasive Computing Applications – Extended Abstract”, ASIACRYPT 2012, Bejing, China, 2-6 Dec 2012

- M. Durmuth, T. Guneysu, M. Kasper, C. Paar, T. Yalcin, R. Zimmermann, “Evaluation of Standardized Password-based Key Derivation against Parallel Processing Platforms”, ESORICS 2012, Pisa, Italy, 13- 14 September 2012

- T. Yalcin, G. Boero, “Single-chip detector for electron spin resonance spectroscopy”, Review of Scientific Instruments 79, 094105 (2008)

- Full list: https://scholar.google.com/citations?user=VXo55fsAAAAJ

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