Yawen Luo

+1-832-***-**** Houston, TX adju6n@r.postjobfree.com linkedin.com/in/Yawen-Luo96

OBJECTIVE

Seeking a full-time position as FPGA/Embedded System/Hardware engineer in related fields

WORK EXPERIENCES

Jun.2019-Aug.2019 FPGA Intern Futurewei Technologies, Inc

State of Polarization Tracking System Prototype

My Duties: Design and implement an FPGA/SoC control system for SOP tracking purpose

•Designed, optimized, and implemented tracking algorithm

•Analyzed and developed firmware for Xilinx FPGAs

•Interfaced FPGA with high-speed A/D, D/A converters, DDR memory, JESD protocol, and I/O

•Completed the integration and testing at a system-level to meet prototype performance requirements

Jun.2018-Aug.2018 Technology Intern Halliburton

Debug of Can Bus Master PCB Failure in Downhole Tool

My Duties: Identify causes of Cold Temp Flash Failures on PCB in some logging tools and fix it

•Analyzed and modified FPGA firmware of the PCB using VHDL

•Implemented testing procedure for flash read, write, and verification

•Searched hardware chip replacements for FPGA

•Conducted experiments to verify the fix of failures

EDUCATION

Doctor of Philosophy, Electrical Engineering Graduating in May. 2021

University of Houston, Houston, TX GPA: 3.85

Bachelor of Science, Electronics and Information Engineering 09/2012-06/2016

University of Electronic Science and Technology of China (UESTC), Sichuan, China GPA: 3.87

SKILLS

Programming Language: Verilog/VHDL, C/C++, Python, MATLAB, Assembly, C#, OpenCL

Software: Quartus, Vivado, Modelsim, Wireshark, VMware Workstation, Matlab, Visual Studio, Eclipse, Putty, Wolfram Mathematica, Cadence, SILVACO, OrCAD

Knowledge:

Machine Learning: data mining, objective function modeling, and classifier training

Experienced with FPGA RTL design, embedded programming, and DSP design

Control system design for high-speed devices: Flash, A/D, and D/A converters

Data Communication Interface: Ethernet, SPI, CAN, UART, I2C, USB, AXI4, PCIe

Computing Networking: TCP/IP, UDP, Wi-Fi 802.11, Bluetooth

Computer Architecture: Cache, Memory, Register, Virtual Memory

Resource management of optical networks

RESEARCH EXPERIENCES

June.2020-present

Hardware Acceleration for Additive Manufacturing Defects Detection

My Duties: Implement FPGA based defects detector in the field of additive manufacturing

•Adopted NEU-DET surface defect database for neural network training purpose

•Employed binarized neural network (BNN) to best-fit FPGA architecture

•Conducted network training on CPU via Python scripts

•Implemented detector on ARM through C++

•Applied acceleration by offloading convolutional layers from ARM to FPGA

Sep.2019-May.2020

Power Efficient Dynamic 3D-Placement of Remote Sensing Drones

My Duties: Propose optimal placement algorithm for drone fleet

•Designed and implemented the 3D-placement algorithm with terrains aware

•Analyzed power model in different modes: communication, hovering, moving, and processing

•Optimized routing scheme within drones aims at power saving

•Proposed a drone location switching scheme to prolong the drone fleet’s lifetime

Jan.2019-May.2019

Mud Pulse Telemetry Speed Up

My Duties: Find available approaches to improve the mud pulse transmission rate of logging tools

• Employed deep learning to suppress noise thanks to huge logging data sets

• Used error correction code to improve the BER

• Applied data compression to improve the transmission rate of MPT

• Utilized digital signal processing techniques to improve SNR

Sep.2018-Dec.2018

Flooding Detection System

My Duties: Achieve data links from flooding area to cloud database and retrieve at clients

•Designed data acquisition circuit with A/D converter

•Applied a Raspberry Pi to pass data to a nearby Router through Bluetooth

•Routed the data to a database (Firebase) through Wi-Fi

•Developed an android application to retrieved information form Firebase

Sep.2017-May.2018

Design of High-Speed Ethernet Communication system with Low-End Processors

My Duties: Responsible for implementing the communication system as a principal researcher

•Devised the entire system architecture, FPGA, ARM, Nand Flash, and Ethernet chip.

•Designed the Nand Flash Memory controller using Verilog

Sep.2016-Agu.2017

Energy-Efficient Fog Computing

My Duties: Study the energy efficiency of Fog Computing (at Cloud edge, targeting end devices)

• Proposed a fog computing-based Smart Traffic Lights System Architecture

• Employed a Genetic Algorithm to manage the Smart Traffic Lights

• Studied fog computing energy consumption by comparing it with cloud computing

• Conducted dynamic modeling and performed a simulation with iFogSim simulator

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