Electrical Engineering

Alaa Abdullah (Altaee), Ph.D., P.Eng.

**** ********* *****, ********* ** L1V 5C1 647-***-****

****.********@*******.**

OBJECTIVE

Looking for the Circuit Technology Engineer 2 position (Requisition Number: 81680) available in your AMD Company in Markham, ON, Canada .

HIGHLIGHTS OF QUALIFICATIONS

• Bachelor, Master of Applied Science, Ph.D. in Electrical and Computer Engineering.

• Thorough knowledge of the overall chip fabrication process.

• Strong working knowledge of electrical circuits, components and circuit analysis.

• Deep understanding of analog and digital transistor device behavior.

• Ability to improve and promote communication, enhance teamwork, problem solving, mentoring and training.

• Able to analyze electrical performance of hybrid Analog/Digital mixed signal designs implemented using deep sub-micron CMOS technology.

• Able to conduct research to find root cause for software and hardware design bugs.

• Skills in using Cadence (Specter analysis, Virtuoso, LVS, DRC, XL layout design), VHDL, H-Spice, P-Spice, Maple, Multisim and Simulink, Quartus II, and Latex.

• Good oral and written communication skills with employees at all levels. EDUCATION

2014 Ph.D. in Electrical and Computer Engineering from Ryerson University, Toronto. 2010 M.A.Sc. in Electrical and Computer Engineering from Ryerson University, Toronto. 1998 B.A.Sc. in Electrical and Communications Engineering from University of Technology, Baghdad.

ACADEMIC HISTORY

2018-2020 Assistant Professor, Georgia Southern University, Georgia-USA. 2015-2018 Assistant Professor, Australian University of Kuwait, Kuwait. 2014-2014 Postdoctoral Research Associate, Ryerson University, Toronto. ACADEMIC EXPERIENCE

Sample of Taught Courses:

• Electric Circuit I: Ohm’s Law, KCL, KVL, Nodal and Mesh Analysis, D.C Circuit Analysis, A.C Circuit Analysis, Half-Wave Rectifier, Full-Wave Rectifier, RL Transient Response, RC Transient Response, and RLC Transient Response.

• Electric Circuit II: Diode, PNP and NPN, BJT Transistor, PMOS and NMOS Transistors, Sizing and pull-up and pull-down Circuits, Op-Amplifier as Summer, integrator, Differentiator, etc.

• Digital Logic Design: Logic Circuit Design in DE2 and Bread Board, Logic Circuit Design Using VHDL Code, Quartus and DE2 Board, and State Machines Design in VHDL and Quartus.

• VLSI Circuits Design: switching noise, mixed analog-digital circuits, modeling of wire channels, clock generation and distribution, power distribution on chip, ESD protection, channel equalization, clock and data recovery.

• Low Power Digital Integrated Circuits Design: Static CMOS, Dynamic CMOS, Transmission Gate, basic logic gates, combinational and sequential circuits, arithmetic building blocks such as adders and decoders, MOS transistor with I-V equations and the different areas of operations, static (DC) and dynamic (transient) behaviors for an important building block and CMOS inverter.

PROFESSIONAL EXPERIENCE

• 1mm/1mm chip layout based on 65nm technology had been fabricated in Canadian Microelectronics Corporation CMC for Adaptive Decision Feedback Equalizer ADFE utilizing Minimum jitter for Gbps serial links in 2014.

• 1mm/1mm chip layout based on 65nm technology had been fabricated in Canadian Microelectronics Corporation CMC for Adaptive Decision Feedback Equalizer ADFE employing Hexagon EOM for Gbps serial links for Gbps serial links in 2014.

• Designed a Power-Efficient CDMA-Based Transmitter for High-Speed Serial Links in Cadence- 65 nm Technology. This project was financially supported by Natural Science and Engineering Research Council of Canada and Computer-Aided Design Tools from CMC Microsystems.

• Designed an RC Model for On-Chip Interconnects in H-Spice.

• Designed a Phase Locked Loop (PLL) in Cadence- 65 nm Technology

• Designed a Full Adder using VHDL Coding and Digital Design Flow.

• Designed a CMOS adaptive engine has a decoder with three charge pumps to provide variable steps control signals for DFE.

• Error detection unit has three CMOS comparators and XOR logic circuit were developed to provide steepest ascent/descent fix control signals.

• 10-PRBS with CMOS differential pair driver, 3-tap DFE architecture with continuous- time liner equalizer CTLE, three separate CMOS charge pumps with fix steps, and three comparators with three sampling points were designed as an Adaptive Decision Feedback Equalizer. The design was simulated and validated using Specter from Cadence in an IBM 65 nm 0.8V CMOS technology.

• CMOS Phase Locked Loop including phase detector, low pass filter and five CMOS quadrature voltage controller oscillator (VCO) cells (ring oscillator) with control circuit were designed and locked. The design was simulated and validated using Specter from Cadence in an IBM 65 nm 0.8V CMOS technology.

POSITIONS IN INDUSTRY

2011-2012 Researcher, Semtech/Snowbush Co., Toronto Presented design techniques for decision feedback equalization of multi-Gbps serial data links: a state-of-the-art review.

Invented of a new hexagon EOM technique to improve the performance of serial links.

2002-2007 Engineering Supervisor, AXA Electric Co.-Toronto. Provided time management for the project.

Involved in the estimation of cost factor for the project. Supervised electricians at the job sites.

1998-2002 Engineering Manager, EIC Co. -Baghdad-Iraq. Supervisor for TV line product.

Supervisor for electronic design group (printed circuit boards). Manager in electronics maintenance department.

PUBLICATIONS

Peer-Reviewed Journal Papers

[1] Alaa Al-Taee and F. Yuan, "An Edge-Based Dual Adaptive Decision Feedback Equalizer for Gbps Serial Links," Analog integrated Circuits and Signal Processing (Springer), Vol.90, No.2, pp.399-409, Feb. 2017.

[2] Alaa R. Al-Taee and F. Yuan, “Adaptive Decision Feedback Equalizer with Hexagon EOM and Jitter Detection”, Circuits, Systems, and Signal processing, Vol. 35, No.7, PP. 2487-2501, Jul. 2016.

[3] A. Al-Taee, F. Yuan and A. Ye, "Adaptive decision feedback equalizer with hexagon EOM and bang-bang jitter detection," Circuits, Devices, and Signal Processing (Springer). Vol.22(3), pp. 373-388, Sept. 2015.

[4] Alaa R. Al-Taee, F. Yuan and A. Ye, "Minimum jitter adaptive decision feedback equalizer for Gbps serial links," IET Journal of Engineering, Vol.2, No.1, pp. 1-7, Jan. 2015.

[5] Alaa R. AL-Taee, F. Yuan, and A. Ye, “An improved RC model for VLSI interconnects with its applications to buffer insertion,” Analog Integrated Circuits and Signal Processing (Springer), Vol.79, No.1, pp. 105-113, April 2014.

[6] F. Yuan, A. Al-Taee, A. Ye, and S. Sadr, "Design techniques for decision feedback equalization of multi-Gbps serial data links: a state-of-the-art review," IET Circuits, Devices,

& Systems. Vol.8, No.2, pp.118-130, 2014.

[7] A. Al-Taee, F. Yuan, A. Ye, and S. Sadr, "New 2D eye-opening monitor for Gbps serial links," IEEE Transactions on Very Large-Scale Integration Systems, Vol.22, No.6, pp. 1209-1218, June 2014.

[8] Alaa R. AL-Taee, F. Yuan, and A. Ye, “A Power-Efficient 2-Dimensional On-Chip Eye-Opening Monitor for Gbps Serial Links,” Analog Integrated Circuits and Signal Processing (Springer), Vol. 76, No. 1, pp. 117-128, July 2013.

[9] Alaa R. AL-Taee, F. Yuan, and A. Ye, “A new power-efficient CDMA-based transmitter for high-speed serial links,” Analog Integrated Circuits and Signal Processing, Vol.71, No.2, pp.1- 7, Feb. 2012.

Papers in Refereed Conference Proceedings

[10] A. Al-Taee, F. Yuan, and A. Ye, "Minimum jitter adaptive decision feedback equalizer for 4 PAM serial links," Proc. IEEE Int'l Symp. on Circuits and Systems, 2015.

[11] Alaa R. AL-Taee, F. Yuan, A. Ye, “A New Adaptive Decision Feedback Equalizer Using Hexagon Eye-Opening Monitor for Multi-Gbps Data Links," IEEE Int'l Symp. on Circuits and Systems (ISCAS), Melbourne VIC, Australia, pp. 2137-2140, June 2014.

[12] A. Al-Taee, F. Yuan, and A. Ye "Two-dimensional eye-opening monitor for serial links," Proc. IEEE Mid-West Symp. Circuits and Systems, pp. 181-184, Columbus, 2013.

[13] A. Al-Taee, F. Yuan, and A. Ye "A new CDMA transmitter for high-speed serial links," Proc. SIECPC-2013, pp.1-4, 2013.

[14] A. Al-Taee, F. Yuan, and A. Ye "A new simple RC modeling for on-chip interconnects with its applications to buffer insertion," Proc. SIECPC-2013, pp.1-4, 2013.

[15] Alaa R. Abdullah, Adnan Kabbani and Kaamran Raahemifar,“ Mapping The AWE-RLC Model Into a Simple RC Circuit With its Application to Buffer Insertion” IEEE Canadian Conference on Electrical and Computer Engineering (CCECE11), pp. 152-155, Niagara Falls, April 2011. PROFESSIONAL MEMBERSHIPS

2018 Professional Engineers of Ontario P.Eng.

2007 Institute of Electrical and Electronics Engineers IEEE. 2006 International Brotherhood of Electrical Worker (IBEW353), Toronto. 1999 Innovative Team in Electronic Industrial Company (EIC), Baghdad, Iraq. 1998 Iraqi Engineers Union, Baghdad, Iraq.

CITIZENSHIP AND LANGUAGE SKILLS

Canadian, fluent in English and Arabic

LICENSE AND CERTIFICATES

2018 Professional Engineers of Ontario License, P.Eng. 2019 TOC., Teaching Online Certificate, Georgia Southern University. 2016 Advanced Diploma in Teaching, Training, and Assessing Learning, The City and Guilds of London Institute.

2004 309A Certificate in Electrical Canadian Code (Ministry of Trade, Toronto-Canada). REFERENCES

Available upon request.

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