Pawan Pandey

A-***, Rahul Nagar,

B-Cabin Road, Tadwadi,

Ambernath (East), Thane,

Maharashtra - 421501.

Mobile: +91-900*******, +91-702*******

Email ID: adjecm@r.postjobfree.com

Objective

To dedicate my sincere efforts for the organization and implement my technical knowledge and skills to enhance my career in the technical domain. Experience

Seagate Technology Sep, 2019 – Present

Designation: Senior Engineer (Physical Design)

Technology: Hierarchical blocks, IO planning, bumping and RDL routing. Skill: ICC2, PrimeTime, Design compiler, Formality, ICV, TCL, Shell.

Experience in handling hierarchical processor blocks from Netlist to GDSII for multiple projects – Synthesis, Constraints, Floor planning, Block partitioning, CTS

& Timing budgeting.

In depth understanding of Block & TOP PnR flow. (Synthesis/Floor planning/Placement/CTS/Routing/Timing/Signoff/Equivalence checking)

Handled IO planning, bumping and RDL routing for 12nm SOC.

Good understanding of STA and timing constraints. Have solid constraint debugging skill, correlation issue and closing of hierarchical and flat timing.

Good at Physical Verification to debug LVS/DRC issues at block/Top level.

Wrote multiple scripts for IO timing budgeting, signal EM flow setup, Icc2 RM script optimization etc.

Have good co-ordination skills to handle IO timing paths between HHM’s and SOC_TOP.

Synopsys (India) Pvt. Ltd. Nov, 2016 – Aug, 2019

Designation: ASIC Physical Design Engr II

Technology: DDR IPs

Skill: ICC2, PrimeTime, Design compiler, Formality, Custom Compiler, Laker, ICV, Calibre, TCL, Python, Shell.

Worked on DDR IPs from RTL2GDSII implementation in cutting edge technologies.

Have hands on experience on PnR, Synthesis, timing closure and signoff.

Worked on high frequency design (6.4 GHz) methodologies in advanced process technologies.

Used Apache Redhawk for Power Integrity. Did RH EM/IR and PV setup for multiple projects. Handle multiple blocks simultaneously.

Have hands on experience of developing standard cells libraries, SRAM IP’s and PDK’s which give extra edge and understanding while handling blocks and signoff.

Proficient in TCL, Python and shell scripting. Wrote multiple scripts which were used across teams.

Worked on automation and scripts to remove manual effort using regexp's, cshell, Tcl and Python.

Wrote scripts for floating metal check, edif.out to layout.oa conversion, manual perforce backup, pin placements, file difference analysis, timing comparision, PnR Errors and Warnings etc.

Broadcom Communications Technologies Pvt. Ltd. Feb, 2014 – Oct, 2016 Broadcom Limited

Designation: R & D IC Design Engineer

Technology: IC Design (VLSI)

Skill: Cadence Virtuoso, Calibre for IC Verification and signoff

Deployed as a contractor for Broadcom Communications Technologies Pvt. Ltd for initial 1 year (Feb, 2014- Feb, 2015) and later absorbed as employee.

Worked on Custom/compiler memory layout designs. Have experience of working on EM/IR, Antenna, decap filling, MPM, SRS, LEF generation and closing of macros/IP (Density fill).

Worked on multi-port register files (e.g. IRU, FPR, GPR,1R4W etc). and single/ pseudo dual port memory development.

Have experience of working on memory compilers for layout development of SRAM memories. Have experience of working on Design check integrity (Device Gain and Signal Coupling) and timing margins.

Worked on Standard cell library development and Gate Array library development.

Worked on 40nm/28nm standard cells to develop layout for clock division circuit.

Worked on 22nm Global Foundry – FDSOI 8T standard cell library development.

Developed 16nm+ 10 track and 8 track standard cell library.

Wrote scripts using SKILL for automating placement of 3*3 row-column standard cells for DRC verification at interface/abutment, scripts to modify bus label for custom IP’s. Worked on compiler memory layout design and tweaking of skill code for memory compiler to add different features and programming. Skills

1. Knowledge of Electronics tools like: ICC2, PrimeTime, Design compiler, Formality, Cadence Virtuoso, Custom Compiler, Laker, ICV, Calibre. 2. Programming Languages: Perl, TCL, Python, Shell & SKILL scripting. 3. Microsoft Office: Word, Excel, PowerPoint.

Achievements

1. Awarded Meritorious Student Award (2007-08) by State bank of India, Nagothane for securing 1

st

rank in HSC at Nagothane.

2. Represented School at district level basketball championship under 14, 17, 19 year categories and won 1

st

prize.

Training

Undergone training in “Study of DCS and PLC” at Reliance Manufacturing Corporation Ltd. (NMD)

Education

Thakur Institute of Career Advancement, Centre for Development of Advanced Computing (CDAC)

PG Diploma in Integrated VLSI and Embedded System Design, CDAC. Passing Grade: A

Datta Meghe College of Engineering

BE Electronics, University of Mumbai.

Passing Grade: First Class with Distinction

J.H.Ambani Vidyamandir College

H. Sc. with Computer Science

Passing Grade: First Class with Distinction

J.H.Ambani Vidyamandir School

Passing Grade: First class

Coursework

Final Year Project: LPG gas detection.

Other Academic Projects:

1. Microcontroller based project to implement Vending machine. 2. Implementation of Arithmetic logic unit in VHDL.

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