Ravendra Mishra adj9pz@r.postjobfree.com

639-***-****

Kanpur, India

linkedin.com/in/ravendra-mishra-188916189

EDUCATION

SKILLS

SIMULATION/EMULATION

&

SYNTHESIS

TOOLS

,

LANGUAGES

English

Hindi

INTERESTS

Travel

Model Sim

Xilinx ISE

PSpice

MS Office

FPGA

C Language

Verilog HDL

Swimming

Cricket

Shooting

Yoga

Passed 10+2

PT. R. P. M. Inter College,Kanpur

(Uttar Pradesh Board)

06/2014 82%

Passed 10

PT. R. P. M. Inter College,Kanpur

(Uttar Pradesh Board)

B.Tech (Electronics & Communication

Engineering)

IET Rohilkhand University,Bareilly

06/2016 – 09/2020 7.45

06/2012 82%

Industrial Vsit

ISRO Telemetry, Tracking and Command

Network(ISTRAC)- ISRO, Lucknow (UP)

ACADEMIC PROJECTS

Trainee

DKOP

Labs

Pvt.

Ltd

VLSI Design Using Verilog and FPGA

6 WEEKS

Verilog HDL Projects

Implementation of High Speed Multiplier Using Vedic Mathematics on FPGA, ATM Machine,Traffic Lights

Controller & Washing Machine

Hardware Projects

IR Proximity

Sensor,Street Light Controller,Water

Level Indicator

TRAINING AND INDUSTRIAL VISIT

PUBLICATION

Implementation of 4- Bit Vedic Multiplier

Using Fredkin and Feynman Gates

International Conference on Academic Research in

Engineering, Managment and Information Technology

(ICAREMIT - 2020) ISBN 978-81-933433-9-5

February 2020 - Available at https://icaremjpru.in/

Contact this candidate