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Mani Tripathi

Gorakhpur,Uttar Pradesh

853-***-**** adj9fi@r.postjobfree.com

Objective

To utilise my skills to contribute towards growth of organisation and enhance my skills further. Education

MJP Rohilkhand University

B.tech

8.11 dgpa

RPM Academy

12th (CBSE Board)

71.6%

RPM Academy

10th(CBSE Board)

8.8 cgpa

INTERNSHIP

DKOP LABS PVT LTD

June,2019- July,2019

Summer Internship

Completed six weeks industrial training in VLSI Design using Verilog HDL and FPGA at DKOP LABS PVT LTD, Noida, U.P.

Projects

Major Project: Pipelined 16-bit Risc Processor using Verilog HDL I have implemented and simulated "Pipelined 16-bit RISC Processor" on modelsim using Verilog Hardware Description Language in which multiple instructions can be executed using a fewer cycle per instruction. Skills

C Programming Language

C++ Programming Language

Verilog Hardware Description Language

FPGA using Xilinx software

Certification Course

C++ Programming language from NIIT

VLSI Design using Verilog HDL and FPGA from DKOP Labs PVT LTD Achievements & Awards

Cultural: Best Performer on Fresher's Day 2k16 in MJP Rohilkhand University Language

English

Hindi

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