TEJAS GOWDA k

Mob: 966-***-****

Email: adj5on@r.postjobfree.com

Career Objective

To be associated with a progressive organization in the Semiconductor Field, that can provide me a Dynamic work sphere for extracting my inherent skills for achieving organization’s objectives and develop my career in the process.

Educational Qualifications

DEGREE YEAR NAME OF INSTITUTE UNIVERSITY PERCENTAGE ASIC Design &

Verification

Intern

2018

Relicuus semiconductors

pvt. Ltd, Bangalore …. ….

B.Tech (ECE) 2018

BGS Institute Of

Technology, Mandya

Visvesvaraya

Technological

University

67%

PUC 2014

BGS independent

Pu College, kunigal

CBSE 69%

SSC 2012

Mahatma Gandhi School,

kunigal

Board Of

Secondary

74.40%

Experience : 10 Months

Currently working as Intern in Relicuus Semiconductor Pvt Ltd doing with AXI express Protocol . VLSI Domain Skills

Operating systems: Linux, Windows

HDLs : Verilog

HVLs : System Verilog

Verification Methodologies : UVM

EDA tools: Aldec, Model Sim, ISE.

Domain: Digital Design,ASIC/FPGA design flow, Methodologies.

Knowledge on: RTL Coding, FSM based Design, simulation, Code Coverage, Functional Coverage, Synthesis, Static Timing Analysis.

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Summary Of Qualifications

Good understanding of ASIC and FPGA design flow

Experience in writing test benches in System Verilog and methodologies like UVM

Experience in using industry standard EDA tools for the front-end design and verification Projects

Project 1 :

UART PROTOCOL :

Platform: Linux Methodology: UVM Tools: Riviera Pro UART is a computer hardware device for asynchronous serial communication in which the data format and transmission speeds are configurable. The electric signaling levels and methods are handled by a driver circuit external to the UART. A UART is usually an individual (or part of an) integrated circuit (IC) used for serial communications over a computer or peripheral device serial port. One or more UART peripherals are commonly integrated in micro-controller chips. A related device, the universal synchronous and asynchronous receiver-transmitter(USART) also supports synchronous operation.

Key features verified in UART protocol:

Understood the UART Protocol Specification

Preparing the Verification Plan

Implementing Test cases

Project 2 :

AMBA AXI3/4 PROTOCOL :

Platform: Linux Methodology: UVM Tools: Riviera Pro The AMBA AXI protocol supports high-performance, high-frequency system designs. Provides separate data and address connections for reads and writes, which allows simultaneous, bidirectional data transfer and verified the protocol using UVM. Key features verified in AXI protocol:

Understood the AXI Protocol Specification

Prepared the Verification Plan

Single Master and Single Slave VIP

Burst mode supported are Increment, Wrap and Fixed

Data transfer for Aligned And Unaligned Address

Implemented Test cases

Constrained Random Stimlus Generation using Sequences

Functional and Code coverage

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Project 3 :

ASYNCHRONOUS FIFO DESIGN AND VERIFICATION:

Platform: Linux Language: Verilog, System Verilog Tools: Riviera Pro An asynchronous FIFO refers to a FIFO design where data values are written to a FIFO buffer from one clock domain and the data values are read from the same FIFO buffer from another clock domain, where the two clock domains are asynchronous to each other. Designed and verified the FIFO for full and empty condition based on the FIFO write and read in Verilog and System Verilog.

Academic Project

Project Title : Smart agricultural management Using IOT Technology.

Project Duration : 4 Months

Designing Model : By using Python simulated & implemented in Xilinx.

Description : Smart Farming is a farming management concept using modern technology to increase the quantity and quality of agricultural products. Farmers in the 21st century have

access to GPS, soil scanning, data management, and Internet of Things technologies. By precisely measuring variations within a field and adapting the strategy accordingly, using Smart Farming techniques, farmers can better monitor the needs of individual animals and adjust their nutrition correspondingly, thereby preventing disease and enhancing herd health. Academic Achievements

Done the seminar on “USB port 3.0 using protocol”.

Project on “Smart agricultural management”.

Paper published in ”International Journal of Advance Engineering and Research Development” (IJAERD).

Personal Traints

Flexible and willingness to accept new challenges,

Desire to learn and update emerging technologies,

Ability to work as a group and individually,

Excellent communication skills,

Enthusiasm to know new technologies.

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Personal Details

Name : TEJAS GOWDA K

Nationality : Indian

Languages : English, Kannada.

Date of Birth : 28-02-1997

Blood Group :

Hobbies : Reading books, Solving Puzzles

Address : Begur cross, near R M C,behind LIC office,Mallagatta kunigal(T), Tumkur(D).

Declaration

I hereby declare that all the above mentioned statements and documents furnished above are true and best to my knowledge and know they can be duly submitted for verification as per employer will.

Place : Bangalore (Tejas gowda k)

Date:

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