Engineer Engineering

D. ANVESH

Contact No: +919********* E-mail:adj56t@r.postjobfree.com

Professional Summary:

Designation: Design & Verification Engineer

Overall 2.1 years of experience in the VLSI industry as Design & Verification engineer.

9 months experience as Assistant Professor in Electronics major VLSI in Kakinada Institute of Engineering and Technology (KIET).

Hands on expertise of verilog, system verilog and UVM.

worked on HBM protocol in Rambus technologies bangalore.

worked on ETHERNET protocol in Asiczen technologies.

worked on AXI protocol in Asiczen technologies

Good understanding on PCI Express,AMBA protocols and Management Data Input/Output

(MDIO).

Skills Set:

Tools : Questasim,VCSsimulator,Cadence,synopsys,Linux,Microwind, DSCH,Xilinx ISE, modelsim,

Languages : C, Verilog, System Verilog.

Methodology : UVM Methodology.

Academic Profile:

• M. Tech in VLSI Design from Kakinada Institute of Engineering and Technology, koringa in 2017 with 71.9%.

• B. Tech in Electronics and Communication Engineering in Pydah College of Engineering and Technology, patavala from board of JNTUK University in 2014 with an aggregate of 64.91%

• Intermediate from Board of Intermediate Education in Sri Chaitanya Junior College, kakinada 2010 with an aggregate of 60%.

● SSC from Board of Secondary Education in S S P V Z P P High school, Patavala, in 2008 with 70.0%

Projects Summary:

AXI UVC Verification using dSim:

CONTRACTOR AT Matric : (Duration: 2019 january to 2019 march) Project -I:

Name : Matric cloud simulator

Client : matric

Description:

Metrics is a cloud-based verification platform, and to use it, your data must reside in the cloud.The mechanism used to get your code into the cloud is the revision control system called git. In order to run a simulation using the Metrics platform, your code must be committed and pushed to a git repository. The Metrics platform includes a web application for test reporting and management, a private source code repository server, and a terminal-based command-line interface.

Responsibilities:

- Understood the basics of dSim simulator.

- Used GitLab for simulation and regression analysis.

- Uploaded the projects into Gitlab and tested the same.

- Verified the bk2bk UVC for two methods of integration required for regression with suitable test cases.

CONTRACTOR AT Rambus: (Duration: 2019 may to 2019 july) Project - II:

Name : HBM PHY Verification

Tools : Questasim,NCverilog,vcs and cadence IMC

Client : Rambus

Description:

The Rambus HBM2E interface is fully compliant with the JEDEC JESD235B standard. It supports data rates up to 3.2 Gbps.The interface features 8 independent channels, each containing 128 bits for a total

data width of 1024 bits.

Responsibilities:

- Understanding of RTL design and Architectural specification.

- made a feature list and verification plan.

- working on functional coverage.

AT Asiczen technologies: (Duration: 2019 august to 2020 may) Project - III:

Name : ETHERNET PHY[400G] UVC Development

Description :

The Ethernet PHY is a component that operates at the physical layer of the OSI network model.PHY module categorized into three layer PCS,PMA,PMD.each layer having receptive functionalities. Responsibilities:

- Understanding the ETHERNET PHY protocol and reviewed feature list extraction.

- Made an architecture document.

Development of PCS layer which includes:

Encoding 64 bit data into 66 bit.

Scrambling 257 bit data.

Forming Alignment markers which are inserted Periodically individual PCS lanes. Development of skew insertion in PMA lanes.

Development of PAM4/NRZ Encoding in the PMA layer. Development of LOW POWER IDEAL [LPI].

Development of new test cases

INTERNSHIP AT Asiczen technologies: (Duration: 6 months) 2018 may to 2018 0ctember Project - IV:

Name : MDIO UVC Development Design Verification in UVM Language : System Verilog

Methodology : UVM

Description:

MDIO is a 2 – wire serial bus used to transfer management information between MAC and PHY. Master and slave agents.

Responsibilities:

- Understood the MDIO specification.

- Made a feature list and verification plan.

- Created architecture document.

- Made testbench/UVC components (driver, monitor and scoreboard) using UVM.

- Made test-cases for testing.

Project - V:

Name : Dual port RAM Verification in

UVM Language : System Verilog

Methodology : UVM

Description:

There will be Two independent ports for (reading and writing) and Multiple writes/reads at the same time.No simultaneous read and write from the same port Responsibilities:

- Understanding the Dual port ram specification

- Created feature list and verification plan

- Coded uvm testbench and test case

- implemented functional coverage

Project - VI:

Name : 4*1 Arbiter Design Verification in UVM

Language : System Verilog

Methodology : UVM

Description:

4 Single bit requests as Input.4 corresponding acknowledgement signals.2 modes for operations (Round robin with fixed priority and Round robin with starvation avoidance). Responsibilities:

- Understood the 4x1 arbiter specification.

- Created feature list and verification plan.

- Designed the RTL.

- Coded testbench and test-cases in Verilog.

- functional coverage

Personal Details:

Date of Birth : 07 – 07 – 1993

Residential Address :patavala,Thallarevu Mandal,East Godavari district,pin-533461 Declaration:

I hereby solemnly declare that the above information is correct to the best of my knowledge. Place: Bhubaneswar

Date:

(ANVESH.D)

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