Kaki Prem Sai

Mobile no :+917*********

Email: adj4ym@r.postjobfree.com

LinkedIn: linkedin.com/in/prem-sai-kaki-0b9257177/ Career objective:

To achieve best possible results by making all possible effort with my skills, while keeping honesty and punctuality at highest priority. I believe that learning is a continuous process. My career should be a means to make my life purposeful. I want to make an indelible and distinct place for myself at my workplace and thereby be a valuable resource for my organization Educational Qualifications:

Sl.no Education stream University/college Year of

passing

Percentage

/CGPA

1. Bachelor of Technology

(B.Tech)

BVC engineering College 2019 70%

2. Higher Secondary

College

Sri Chaitanya Junior college 2015 90%

3. Matriculation/SSLC Sri Chaitanya Techno School 2013 9.2 Certification course:

Advanced VLSI Design and Verification course

Maven Silicon VLSI Design and Training Centre, Bangalore https://www.maven-silicon.com/

June 12 till date.

Technical skills:

VLSI Domain skills:

HDL: Verilog

HVL: System Verilog

Verification methodology: Coverage driven verification, Assertion based verification TB Methodology: UVM

EDA Tools: Questa-Sim – Mentor Graphics

Riviera Pro – Aldec

ISE - Xilinx

Domain: ASIC/FPGA front-end Design and Verification Knowledge: RTL Coding, FSM based design, Simulation, Code Coverage, Functional Coverage, Synthesis, Static Timing Analysis, ABV- SVA Projects:

Router 1x3 – RTL design and Verification

HDL: Verilog

HVL: System Verilog

TB Methodology: UVM

EDA Tools: Questa-Sim and ISE

Description: The router accepts data packets on a single 8-bit port and routes them to one of the three output channels, channel0, channel1 and channel2. Responsibilities:

Architected the block level structure for the design.

Implemented RTL using Verilog HDL.

Architected the class-based verification environment using System Verilog.

Verified the RTL model using System Verilog.

Generated functional and code coverage for the RTL verification sign-off.

Synthesized the design.

SPI Controller Core – Verification:

HVL: System Verilog

TB Methodology: UVM

EDA Tools: Questa-Sim

Description: The SPI IP Core provides serial communication capabilities with external device of variable length of transfer word. This Core can be configured to connect with 32 slaves. Responsibilities:

Architected the class-based verification environment using System Verilog.

Defined Verification Plant.

Verified the RTL module using UVM.

Generated functional and code coverage for the SPI Controller Core. Academic projects:

“Density based traffic light control using Arduino-Uno” – In the proposed system by using the image processing along with the Arduino-Uno, the vehicle count is measured, Emergency vehicles like Ambulance and fire-engines are easily allowed from the traffic by using the RF transmitter and receiver .

- B.Tech Project

Strengths/Behavioral skills:

Flexibility

Determination

Self-Control

Hobbies:

Watching and playing cricket

I like to spend time with people to learn new things

Plantation

Declaration :

I do hereby declare that above particulars of information and facts stated are true, correct and complete to the best of my knowledge and belief. Date:

Place: (Kaki Prem Sai)

Contact this candidate