NAGA SIVA PRASAD YAMMUNURI

Phone Number: +91-957*******

Email:-adj4y3@r.postjobfree.com

CAREER OBJECTIVE :

To obtain a position that will allow me to utilize my technical skills, experience and willingness to learn in making an organization successful. Academic Details:

Graduation

College / School Year Of

Passing

Percentage

B.Tech (Electronics

& Communication

Engineering)

Vikas group of institutions,

Vijayawada

2020

7.3 (CGPA)

Intermediate

rayalaseema junior college,

Tirupathi

2016

89%

SSC

Sri chakra high school,

Rayachoty

2014

9.7 (GPA)

TECHNICAL SKILLS :

• PROGRAMMING LANGUAGES: TCL.

• TOOLS: IC Compiler, Primetime, Verilog programming in Xilinx.

• CONCEPTS: Physical Design, STA, CTS, Digital electronics, .

• DESIGNING: Digital Modules, State machines, Physical Design (PnR) project in IC Compiler.

COMPETENCIES :

• Finished a course as Physical Design Engineer Trainee in Takshila Institute of VLSI Technologies.

• Good understanding of block level Physical design concepts.

• Practical exposure to Physical design tools from ICC II/ICC Compiler, Primetime, Design Compiler tools.

• Have a thorough knowledge on all stages of place and route flow from netlist to GDS.

• Worked on timing closure of critical blocks.

• Understanding of various timing reports during STA.

• Worked on 32nm chips.

• Good Working knowledge of Linux and understanding of TCL script.

• Deep comprehension of various Physical Design concepts including data flow diagram, cross talk, electromigration, local and global skew. PROJECTS :

1. Physical Design :

Domain: Physical Design, IC Compiler

Title Project 1

Tool Used IC Compiler, Primetime

Description Technology : 32 nm

No.of Macros : 40

No.of Std. Cells : 52000

Metal Layers : 8

Frequency : 416 MHz

No.of Clocks : 8

Responsibilities Floor planning, Power planning, Placement and CTS, Routing and DRC checks.

Challenges Iterative Floor planning, solving global routing congestion after placement, solving timing violations in post-placement stage. Solving timing violations in post CTS (hold), congestion in post routing stage.

2. Physical Design :

Domain: Physical Design, IC Compiler

Title Project 2

Tool Used IC Compiler, Primetime

Description Technology : 32 nm

No.of Macros : 50

No.of Std. Cells : 68000

Metal Layers : 8

Frequency : 433 MHz

No.of Clocks : 8

Responsibilities Floor planning, Power planning, Placement and CTS, Routing and DRC checks.

Challenges Iterative Floor planning, solving global routing congestion after placement, solving timing violations in post-placement stage. Solving timing violations in post CTS (hold), congestion in post routing stage.

3.Academic Project:

Smart electronic notice board:-

Smart electronic notice board is an digital process to display on notice boards, like timetables, student attendence

Smart electronic notice board is used for time conservative and uses to reduce human work.

Tools used:-

Arm processors

Arduino

Leds

Connecting wires

PERSONAL DETAILS :

Name :- Naga siva prasad Yammunuri

Father Name :- Venkata ramana Yammunuri

Date of Birth :- 15-6-1999

Language Known :- English, Hindi & Telugu

Nationality :- Indian

Interest & Hobbies :- Internet browsing,dance, badminton DECLARATION:

I declare that the information given above is true to the best of my knowledge. Yours truly

Place: Bengaluru, Karnataka (Naga siva prasad yammunuri)

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