Engineer Engineering

B. PRABHANDA EMAIL: ***********@*****.***

Phone number : 809-***-****

Objective

To secure a challenging position where I can effectively contribute my skills as DFT professional.

TECHNICAL SUMMARY

Good knowledge on Scan insertion & ATPG

Good knowledge on compression, OCC, JTAG & MBIST

Basic knowledge on Verilog & STA.

Current Profession

Design for Testability (DFT) training from VLSIGURU training centre, Bangalore, using Mentor tools. Duration: June 2019 – till-to-date.

DFT course outline

SOC Flow, DFT Basic and fundamentals, SCAN Architecture, SCAN DRC, SCAN Insertion, Compression Insertion, Boundary Scan, JTAG, ATPG Faults, Fault models, ATPG Coverage, ATPG for stuck-at and Transition fault models and pattern simulations. Projects Summary

Project 1: ”DMA_ TOP”

Design: Design with about 100k flops

No. of clocks: 2

No. of scan channels: 8

Tools Used: TessentScan, TestKompress, Design Compiler & Tessent Fastscan,Questasim Role: Performed scan Insertion, analyzed DRCs & fixed. Performed compression logic insertion. Generated patterns for both Stuck-at & At-speed and validate the patterns. Project 2: ”Test_block”

Design: Design with about 60k flops

No. of clocks: 3

No. of scan channels: 10

Tools used: TessentScan, and TestKompress, Design Compiler & Tessent Fastscan, Questasim Role: Performed scan insertion, analyzed DRC’s & fixed. Performed compression logic insertion. Generated patterns for both Stuck-at & At-speed and validate the patterns. Project 3: ATPG pattern generation/simulation for Stuck-at and Transition Fault models. Design: Design with about 85k flops

No. of clocks: 2

Tools Used: Tessent Fastscan, Questasim

Role: Generated patterns for both Stuck-at and Transition fault models. Generated Basic and sequential patterns using Tessent FastScan. Worked on coverage analysis. Validated both Chain and Logic patterns

Education:

Completed Bachelor of Technology, Electronics and Communication Engineering with percentage – 72 in 2019 from Audisanakara Institute of Technology, Gudur, Nellore, Andhra Pradesh.

Completed Intermediate (M.P.C) with percentage – 93.4 in 2015 from state board of intermediate education, Tirupathi, Chittor, Andhra Pradesh.

Completed secondary school education with percentage – 90 in 2013 from board of secondary education, Rajampet, Kadapa, Andhra pradesh.

PERSONAL DETAILS

DATE OF BIRTH : 24 April, 1998

NATIONALITY : Indian

GENDER : Female

PERMANENT ADDRESS :D.No:8/4/b,chinnellugaripalli(vi),rajampet(md),kadapa(dt) LANGUAGES KNOWN : English, Telugu

DECLARATION

I here by declare that the information given above is true to the best of my knowledge. DATE : Signature

Place : Bangalore (B. prabhanda)

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