RESUME

Name : Chandrasekharachari. S

Email id : adj4rk@r.postjobfree.com

Phone : +91-950*******

Summary:

• Having 1.1+ years of experience as Associate Analyst in GlobalLogic technologies.

• 11 months of experience as freelance functional tester.

• 3 months of experience as freelance recruiter for semiconductor domain.

• I have 1 yearear Internship experience on VLSI Physical design in Sion semiconductors.

• Good knowledge in Floor planning, Placement and Routing, Clock tree synthesis and basics of STA.

• Good knowledge in ASIC flow and Physical design flow.

• Good knowledge in basics of digital electronics, cmos and VLSI concepts.

• Knowledge in manual and automation testing using selenium.

• Knowledge on Test Scenarios, Test cases and Test data.

• Good Knowledge in Integration of SDLC, STLC, BLC and ALC processes in project based and product based software’s like websites and web services, Window based and Mobile apps.

• Worked in Waymo process and good working knowledge on Video labelling, Image labelling and data annotation.

• Working knowledge on self driving car process.

Educational Qualifications:

• Completed B.Tech in E.C.E at SSIET, Nuzvid from JNTU Kakinada –2016 with 67%.

• Completed Diploma in ECE at AANM & VVRSR Polytechnic from Gudlavalleru – 2013 with 80%.

• Completed S.S.C from Sri Chaitanya Public school from Vissannapeta – 2009 with 74% Technical Skills:

Operating System : Linux

Languages : Perl, TCL (basics).

Tools : Mentor graphics(Oasys and Nitro SOC), Qflow, Synopsys IC compiler, LTspice, eSim, Kicad. Projects:

Project Title : Open source power analysis tool

Role : Involved in research of power analysis tool and its applications in low power VLSI design, analyzing the input and out put power, developing the automated script. Project Title : ADC controller

Tool used : Mentor graphics (Nitro_Soc)

Gate count : 149692 Total STD cell area : 21629.4 µm Core utilization : 70.18% No. of clocks : 2

Clock Frequency : 300 MHz Technology : 250nm

Role : Involved in performing sanity checks, designing export, preparing floor plan, power plan, placement, trail route and detail routing.

Project Title : PLIC

Tool used : Qflow Total STD area : 720557.31 µm

Gate count : 56299 Clock Frequency : 116.213MHz

Core Utilization : 50 % Technology : 180nm

Role: Involved in performing sanity checks, designing export, preparing floor plan, placement, trail route and detail routing.

Project Title : ORCA_TOP

Tools used : Synopsys IC compiler

Gate count : 33303 Total STD cell area :71084.560µm Core utilization : 70.2% No. of clocks :5

Clock Frequency : 500 MHZ Technology :28nm

Role : Involved in performing sanity checks, designing export, preparing floor plan, power plan, placement, CTS and routing.

Achievements:

• I have participated on one day work shop in ENTERPRENEURSHIP DEVELOPMENT by THE NATIONAL SMALL INDUSTRIES CORPORATION LTD (A Government of India Enterprise).

• I have participated in a Two Days workshop on the ARM Processor and its Applications conducted by department of ECE, Usha Rama College of Engineering and Technology.

• I have participated in a Two Days workshop on the Low Power VLSI using Tanner conducted by Pantech Pro Ed Pvt Ltd.

• I have participated in the District level Chess competition and dance competition in our college.

• Agile SCRUM certification.

• I have participated on 5 days online workshop in VLSI SYSTEM DESIGN USING OPEN SOURCE EDA conducted by IIT GUWAHATI.

Personal Details:

Father’s Name : S. Anantakotisivaprasad

Permanent Address : D. No:-4-64, Tatakuntla,

Vissannapeta (MD), Krishna (dt), (A.P).PIN-521215

Declaration:

I hereby declare that the information furnished above is true and correct to the best of my knowledge. Date: Signature

Place:

(S.CHANDRASEKHARACHARI)

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