ALOK KUMAR PATHAK

Address : F-***, Sonam Unique, New Golden Nest, Phase-10, Bhayandar-East, 401105

https://www.linkedin.com/in/alok-kumar-pathak-b12498117/ https://github.com/Alok1998

+919********* adj1pe@r.postjobfree.com DOB: 05-JAN-1998 BRIEF OVERVIEW

XM.Tech in VLSI AND EMBEDDED SYSTEMS from College Of Engineering Pune. XStrong Knowledge of Analog IC Design and Digital Circuit Design and Device Physics. XGood understanding of methodologies of Floor-Planning, PnR, Timing closure and Physical veri cation. XGood Knowledge of verilog, c programming and TCL scripting. XFamiliar with Static and dynamic power dissipation, low power design techniques. XSelf-motivated, Hardworking and always curious to learn new things. EDUCATION

M.Tech in VLSI and Embedded Systems, College Of Engineering Pune, with CGPA 7.34/10. 2018-2020

B.E in Electronics and Telecommunication, University of Mumbai, with CGPA of 8.56/10. 2014 - 2018

Class XII (Intermediate) from National Inter College, Board of High School and Intermediate Education Uttar Pradesh with 81%. 2014

Class X (SSC) from National Inter College, Board of High School and Intermediate Education Uttar Pradesh with 86%. 2012

TOOLS & LANGUAGES

Programming Languages: C, TCL Basics, Verilog, TL-Verilog. Tools/Software: Cadence virtuoso, Matlab, LTspice. Open source EDA Tools: Ngspice(spice sim.), OpenTimer(STA), Q ow(tool chain for digital circuits). Operating System: Windows, Linux

TECHNICAL EXPERTISE

XDevice Physics

XAnalog IC Design

XDigital circuit Design with verilog

XDigital Signal Processing

XStatic Timing Analysis

ACADEMIC PROJECTS

M.TECH MAJOR PROJECT Design of 100mV Low-Dropout Voltage Regulator having Fast Transient Re- sponse. SEPT 2019- MARCH 2020

In this design work, A Low dropout voltage regulator is designed using gpdk 180nm technology on cadence tools. The designed LDO works under the input voltage of 2-1.8 V and settled to constant output voltage of 1.7v with settling time of 20us. The LDO has undershoot and overshoot of 62mV and 73mV under a step load current of 20mA.The quiescent current of LDO is 111.1uA.

M.TECH MINI PROJECT Design of 6T-SRAM circuit. JAN 2019- FEB 2019 In this mini project, A 6T sram cicuit has been designed using gpdk 180nm technology on cadence tools. The power dissipation and delay of designed sram cell are 54.63nW, 19ns. M.TECH MINI PROJECT Design of a Folded cascode OTA circuit of high gain and phase margin SEPT 2019-NOV2019.

In this design work, An folded cascode OTA has been designed using gpdk 180nm technology on cadence tools which has gain, phase margin, UGB, slew rate, CMRR and power dissipation of 60dB, 89deg, 13MHz, 8.91v/us, 105dB and 3mW respectively. B.E MAJOR PROJECT Electromagnetic rocket launcher for fast take o with password security AUG 2017- APR 2018.

The aim of this project is to design and construct single and multi stage coil guns capable of ring projectiles at a high speed

(6m/S). In this project, An Atmega 16 uc, a coil gun, a keypad, a LCD, a relay, a transistor and a capacitor bank are used. CERTIFICATION

Successfully completed the online Training Program on \VLSI SYSTEM DESIGN USING OPEN SOURCE EDA" with grade \A" organized by EICT Academy IIT Guwahati held from 23-27 September, 2019 in association with VLSI System Design(VSD) Corp.pvt.Ltd.

Successfully completed VSD Physical design ow course available on udemy.

Successfully completed VSD Static Timing Analysis course available on udemy.

Successfully completed the "Design of RISC-V based CPU using TL-verilog". CURRICULAR ACTIVITIES

Worked as a Teaching Assistant at COEP,Pune. My responsibility was taking a Digital CMOS Design Lab of B.Tech nal year and M.Tech rst year students.

SOFT SKILLS

Fluent in Hindi and English.

DECLARATION

I hereby declare that the information and facts stated above are true and correct to the best of my knowledge and belief. Thanks & Regards,

Alok Kumar Pathak

Contact this candidate