ARJUN SHINDE

M.Tech – VLSI DESIGN - IIT, Dhanbad.

# 19MT0081 adj1ci@r.postjobfree.com

+91-727*******

E-mail: adj1ci@r.postjobfree.com Skype: .cid.a0f76312332576e1 Skype id: adj1ci@r.postjobfree.com

PROJECTS

1. Implementation and Analysis of Reversible

digital circuits using Quantum Computing.

[M.Tech Thesis](on Going)

Organization/ Institute - IIT Dhanbad.

Description - To perform the analysis and implementation of reversible digital circuits on quantum interface, Develop an ALU circuit using reversible gates on Quantum Interface. The project is carried out using Python Programming language. So as to make digital circuits more optimized and efficient. Tools &Technology - Qiskit.

2. Verification Architecture for

combinational and sequential circuits.

Organization/ Institute – SION Semiconductors.

Description - An optimized verification architecture was developed for the verification of digital circuits in place of using separate test cases for the verification of circuits. The architecture was implemented for the circuits like SRAM, Asynchronous FIFO.

Tools &Technology – Questa Sim.

3. Automatic Floor Cleaning Bot.

Organization/ Institute –Shri Ramdeobaba College of Engineering

Description - The bot has the functionality of wet cleaning as well as dry cleaning along with detachable vacuum suction nozzle. The bot is controlled by any android device by Bluetooth connectivity. Bot can be used on supply or with its rechargeable Li-ion battery with 24v compatible charger of 2A smps with dc jack. The project is done using microcontroller ATmega 328P.

Challenges - To design a model which should be capable of performing wet as well as dry cleaning. Also, to create a appropriate vacuum pressure for dry cleaning operation. INTERNSHIP

Role – SOC Verification Intern.

Duration – June 2020 to December 2020 (Tentative). Group – High Speed interfaces.

SKILLS AND EDA EXPOSURE

● Programming: Verilog, Sysem Verilog,

Python (Qiskit).

● Tools: Xilinx ISE, QuestaSim, Silvaco TCAD

(device modelling), Multisim, Vivado, Cadence

Virtuoso.

● Methodology: UVM.

EDUCATION

Indian Institute of Technology (ISM),

Dhanbad — ( M.Tech) VLSI DESIGN

JULY 2019 - MAY 2021 OGPA – 7.25

Shri Ramdeobaba college of Engineering

Nagpur — ( B.E. ) ELECTRONICS ENGINEERING

JULY 2015 - MAY 2019 CGPA – 8.4

School

12th - APRIL 2014 - APRIL 2015 – 79.38%

10th - APRIL 2012 - APRIL 2013 – 9.4 (CGPA)

ACHIEVEMENTS

● Parshuram Baji Agashe science innovation award-

2017(1st prize) at mumbai in competition organized by Marathi vidnyan parishad.

● Secured AIR 1286 in GATE 2019

● Got selected in Raman festival of innovation to

present project in innovation exhibition.

EXTRACURRICULARS

● Contributed in TECH TALK on quantum

computing organized by IEEE student chapter of

BIT mesra in 2020.

● Passed the ELEMENTARY drawing grade

examination held in year 2009.

● Appreciation certificate for outstanding

performance in speed Maths contest held in year

2012.

● Secured 3rd runner up position in drawing

competition organized by genius kid SIP Abacus on

interschool level.

● Participated in Autobot in axis 16 the annual

technical festival of VNIT Nagpur.

Contact this candidate