Design Engineering

PRAJWAL MUDALAMANE GURUMURTHY

***********@*****.*** 469-***-**** linkedin.com/in/prajwal-m-g

SUMMARY

An enthusiast Master’s student looking forward for an opportunity to apply my knowledge and skills to contribute in the field of Digital Circuit design, Physical design, Layout design and Digital Verification roles. EDUCATION

Masters of Science, Electrical Engineering Jan 2020 - Dec 2021 The University of Texas at Dallas GPA: 4.0

Bachelors of Engineering, Electrical and Electronics Engineering Aug 2015 - May 2019 The National Institute of Engineering GPA: 8.64

SKILLS

RTL Design: Verilog HDL, Verilog, SystemVerilog, UVM Programming languages: C, C++.

EDA Tools: Synopsys Design Compiler, Xilinx ISE Design Suite, Xilinx Vivado, Mentor Graphics, Modelsim, Altium Designer.

Assembly language: 8085

Scripting language: Python, PERL

Courses: Advance Digital Logic Design, Computer Architecture, Wireless Sensor and Networks, VLSI Design, ASIC Design, Testing and Testable Design.

EXPERIENCE

Gradute Student Assistant, Texas Analog Center of Excellence Nov 2020 - Present

• Currently working on circuit design of piezo-electric energy harvester.

• Working on the PCB design of the energy harvester circuit. Intern, ADR CONTROLS LLP Jun 2018 - Jul 2018

• -Trained on Miniature Circuit Breakers, Vacuum Circuit Breaker and Air Circuit breakers.

• -Worked on variable speed drives and acquired skill in ladder programming for PLC.

• -Practical knowledge on Star-Delta starter, Direct On-line Starter and Soft Starter. Intern, Bharath Electronics Limited Jun 2017 - Jul 2017

• -Worked on Switch Mode Power Supplies and Transformers.

• -Designed and simulated on different DC to DC Converters. PROJECTS

Design of Low Power Approximate Adder

• The project was aimed to design a low power consuming and energy efficient approximate adders.

• As the approximate adders are used for DSP applications. The approximate adders are used in the LSB bits of the compressors in order to maintain the accuracy and output quality of the compressors. We proposed different versions of Mirror Adder Cells to ensure minimum errors in Full Adder. Design and Implementation of MIPS32 Pipeline

• Implemented MIPS32 pipeline through behavioral modelling through verilog code.

• The code was simulated in the Xilinx Vivado tool and verified by developing the test bench and comparing the results. Design and Implementation of Mini Stereo Digital Audio Processor

• Tools used: Xilinx ISE, Design Compiler, IC Compiler, Virtuoso

• Languages: Verilog, C

• Coded convolution algorithm as a series of shift-add operations in C and behavioral style Verilog as a prototype.

• Developed system specifications and architecture, signal formats, state machine, operating modes, and frequencies for final implementation as RTL Verilog code using Xilinx ISE.

• Performed synthesis and STA using Design Compiler and post-synthesis testing using Xilinx ISE.

• Carried out APR and final layout using Synopsys IC Compiler, which was optimized for area and power, and then checked for DRC and LVS.

32-bit Arithmetic Logic Unit Design using 65nm Technology

• Using the Verilog file written for ALU and the library file generated from SiliconSmart ACE, the Gate-level netlist for the design was created using Design Vision.

• Automatic Placement and Route was carried out in Cadence Innovus using the synthesized Verilog file.

• Imported the routed design to Cadence Virtuoso; DRC & LVS were cleared; Static Timing Analysis was run using Synopsys Primetime.

• Effectively optimized the layouts to minimize area, using 65nm technology CERTIFICATION

• Certification by cadence on Systemverilog Accelerated verification with UVM v1.2.

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