Assistant Design

Sai Yarragunta adir5x@r.postjobfree.com 781-***-****

*** * ***** **, ****** Creek, CA 94596

TECHNICAL SKILLS

• Proficient in CMOS circuit design and layout using Cadence IC Design Suite

• Testing – Digital & Mixed Signal VLSI Circuits

• Verification using System Verilog in UVM

• Softwares and tools: Model Sim, NC Sim, Xilinx ISE, Vivado, LTSpice, Tine-TI.

• Allegro, Altium, COMSOL, LabVIEW and ADS

• RTL Designing using Verilog/VHDL

• Programming in C, C++, Python and MATLAB

• Electronic Test Equipment (Oscilloscope, Logic Analyzer, etc)

• CAD modelling and 3D printing

EDUCATION

• Master of Science in Computer Engineering GPA: 3.6/4.0 August 2020 University of Massachusetts Lowell, Lowell, MA

• Bachelor of Technology in Electronics and Communications Engineering May 2018 Sreenidhi Institute of Science and Technology, Jawaharlal Nehru Technological University, Ghatkesar, India EXPERIENCE

Graduate Teaching Assistant Spring 2020

VLSI Fabrication/Nanofabrication Lab, UML, Lowell, MA

• Trained students in a Clean-room environment (Class 100) for Semiconductor processing steps like Thermal oxidation, Photolithography, Diffusion, Etching and Metallization

• Assisted graduate students in fabricating an npn-transistor on a 3-inch Silicon wafer. Trained students to use industry level equipment like Ellipsometer, Mask Aligner, Micromanipulator. Graduate Teaching Assistant Fall 2019

VLSI Design/VLSI Lab, UML, Lowell, MA

• Trained students to use and build basic circuits in Cadence. Training also includes efficient floor planning for layout design, simulating results in different operating conditions like temperature.

• Guided to develop CMOS circuits – Counters, Multipliers, RAM

• Assisted students for lab projects and graded for VLSI design lab weekly tasks Project Assistant Summer 2017

Ordnance Factory, Medak, India

• Reverse engineered an analog-based control board to implement a digital electronics version which was more efficient and cost-effective.

ACADEMIC PROJECTS

Graduate Academic Projects, UML, Lowell, MA 2018-2020

• Designed, built, and soldered a functional Op-Amp within the required parameters for a design contest. Placed second in the contest with a voltage gain of 530K.

• Designed a Digital Lock using state machines and a Code Converter using advanced logic design techniques.

• Submitted an academic project on carry lookahead adder circuit using CMOS 90nm technology in Cadence. Undergraduate Academic Projects, JNTU, Hyderabad, India 2014 - 2018

• A mini project report on “Design of SHA-3 Algorithm using Verilog”.

• Presented a technical seminar on “Simultaneous Wireless Information and Power Transfer (SWIPT)”.

• Designed, built, and tested digital circuits on prototype FPGA boards - Counters, Multipliers, RAM. THESIS & PUBLICATIONS

• Master’s Thesis: “G-band Double Balanced Mixer in Tandem with High-Speed ADC for Baseband Signal Processing in RF Communication Systems”

• Published a paper in an open access International Journal Current Research (IJCR) titled “FPGA Implementation of Enhanced SHA 192 Algorithm,” Volume 9, Issue 12, Page no. 586**-*****

• Presented a paper at National Conference on Signal Processing & Communication 2018 titled “IOT Based Smart Garden Monitoring System”.

Contact this candidate