Ruthvik Kuram

**** * ******** **, ******, AZ, ***12 adips9@r.postjobfree.com 513-***-**** LinkedIn Profile GitHub PROFESSIONAL SUMMARY

Passionate about developing reliable and efficient ASIC designs by leveraging strong programming skills and hands-on experience in VLSI physical design, CAD, and testing tools. EDUCATION

Master’s in Electrical Engineering GPA: 3.78/4.00

University of Cincinnati, Cincinnati, Ohio

Courses: VLSI design and automation, VLSI low power design and testing, Embedded systems, Advance Microcontroller design, Hardware Trust and Security, Advance Probability theory, Linear systems. Bachelor of Technology in Electronics and Communication Engineering GPA: 3.33/4.00 GITAM University, Visakhapatnam, Andhra Pradesh, India Courses: Analog and Digital circuit design, Computer Architecture, Digital Signal Processing, Wireless/Mobile Communications and Networks, Antenna and Wave Propagation, VLSI Design through Verilog. SKILL SET

• Technical: Physical Design, Digital Circuit Design, ASIC Design and Testing, Design Automation, Formal and Functional Verification, Fault modeling, Placement & Route, RTL Design and Synthesis, DFT, BIST, MBIST, JTAG, ATPG, Boundary scan chain, Model checking, Timing fix, Static Timing Analysis, OVM/UVM, CDC, CTS, Power and Memory optimization, DRC and LVS.

• Programming Languages: VHDL, System Verilog, Verilog, TL-Verilog, C, C++, Python, MATLAB, Visual Basic, Perl, Tcl.

• EDA and Simulation Tools: Synopsys Design, BSD and Power compiler, TetraMAX, HSPICE, IRSIM, ModelSim, ALTERA Quartus, MPLAB X, NuSMV, CVAVR, Arduino, KeilVision, STM32CubemX, LabView, Proteus, Magic, Yosys open synthesis suite, ABC, Graywolf, Opentimer and OpenSTA, Qrouter and TritonRoute, ngSPICE, esim, Fault. EXPERIENCE

Graduate Teaching Assistant, University of Cincinnati, OH 08/2018 – 12/2019

• Teaching students to develop critical thinking skills through algorithmic approach and team discussions.

• Provided firsthand training on engineering tools like Excel, Python, LabView, MATLAB, Visual Basic, CAD and Rapid Prototyping.

• Coordinated peer mentor program by providing and managing mentors to over 300 students and planning project events.

Graduate Research Assistant, University of Cincinnati, OH 11/2017 – 06/2018 Project – Design of Semi-Autonomous Robot

• Designed a wireless omnidirectional robot using Raspberry Pi and sensors like IMU, 360o laser scanner and camera for LIDAR mapping and sonar-based applications implementing machine learning algorithms.

• Implemented Proteus tool to design a custom sonar DAQ circuit to generate and capture echoes.

• Optimized the circuit further by integrating all the sensors into a single PCB board using tools like oscilloscopes and probes.

WORKSHOPS

Physical Design using OpenLANE flow on Skywater130 PDK 10/2020 – 11/2020

• Physical design flow using OpenLANE flow with open-source tools configured to Google-Skywater130nm open source PDK on RISC-V architecture based PicoRV32 core.

• Performed RTL synthesis and technology mapping on Yosys open synthesis suite and ABC tool using Tcl scripts.

• Executed floor planning and placement of standard cells along with IO horizontal and vertical metals, decap cells, and tap cells insertions.

• Analyzed the change in rise and fall delay values by varying the width of pmos and load capacitance using ngSPICE simulations.

• Designed a custom inverter cell and implemented into the main design by merging .lef files and analyzed the design in Magic editor using Sky130 tech files along with the respective .lef, .def files at each stage.

• Implemented CTS on the synthesized Verilog files and performed STA using openSTA at each stage of the design flow reducing setup and hold slack by changing the variables of buffer size, driving cell load, buffer fan out, and synthesize strategy with respective .db, .sdc, library and Verilog files.

• Generated Power distribution network and performed routing using Qrouter for global routing and TritonRoute for detailed routing.

• Extracted the SPEF file from the def file and performed DRC and LVS on the layout using ngSpice simulations. RISC-V Microarchitecture Core Design 11/2020 – 12/2020

• Designed a pipelined RISC-V microarchitecture core based on base integer RV32I instruction format using Transaction Level Verilog on Makerchip IDE.

• Compiled and disassembled the Hexadecimal calculator code using RISC-V GNU compiler toolchain.

• Implemented the CPU core with Fetch, Decode, Register read/write, Branch and Data Memory load/store blocks into 5-staged pipelined structure.

• Implemented Register File Bypass to counter register read/write hazards and counter the branch target hazards by speculating the subsequent instruction.

ACADEMIC PROJECTS

Synthesis, Scan Chain Insertion, BSD and ATPG 01/2017 – 03/2017

• Synthesized an RTL design of GCD and Fibonacci machines into gate-level using Synopsys Design Compiler by developing timing constraints for having maximum speed and insertion of scan chains for testability. Implemented using Tcl scripts.

• Constructed an internal scan and boundary scan chains by inserting TAP controller using Synopsys BSD compiler.

• Generated ATPG patterns on TetraMAX tool to verify the design for stuck-at-faults and achieved 98% fault coverage.

Design Automation for Balanced Bi-Partitioning 01/2017 – 03/2017

• Implemented Kernighan-Lin and Simulated Annealing algorithms on netlists resulting in minimal-cost partition using C++.

• Optimized the algorithm for minimum memory usage and achieved a minimum cost cut with efficient run time and simulation results on larger benchmarks as many as 45000 cells with 450000 nets. Design Automation for Placement and Routing 01/2017 – 03/2017

• Implemented the Force Directed algorithm for placement of cells and Channel Routing algorithm to route the netlists between the standard cells. Developed using C++ in Linux environment.

• Optimized the algorithms to manage larger benchmarks of order 1000 nets and cells.

• Achieved optimum results with 83% reduction in total wirelength and 100% routing with efficient run time. Dual-Level Power Estimation and Gate-Level Power Optimization 02/2017 – 03/2017

• Generated VCD files from RTL design and synthesized gate level design using ModelSim and converted it to SAIF file.

• Analyzed the power consumptions between RTL and gate-level GCD machine. Performed logic-level power optimizations using multi-threshold gate libraries to reduce dynamic and leakage power constraints using Synopsys Power Compiler.

Post Silicon Validation (Chip Testing) 02/2017

• The fabricated Programmable Interconnect Network IC is tested using HP Agilent logic analyzer at 100Mhz.

• The chip functionality and scan chains inserted are tested including corner test cases concluding a 100% fault free chip.

ASIC Design of Programmable Interconnect Network (Bit sliced approach) 11/2016 – 12/2016

• RTL design in Verilog, ModelSim/Spice and IRSIM simulations, Test logic insertion, timing Analysis, DRC fixes, Tape out, Placement and routing in Magic editor.

• Optimized for maximum area with 14-bit slices and maximum testability and scalability.

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