Engineering Design

Schematic Capture :

Virtuoso Schematic

Physical Layout :

Virtuoso

Platforms : Windows,

LINUX

*************@*****.***

830-***-****

**/*** **-***** ** Mayur

Talkies Naina Garh

Road Morena-476001

SKILLS

EDUCATION

M.Tech [Microelectronics & VLSI Design]

SGSITS Indore

2017 – 2019

B.E [Electronics & Communication Engineering]

78.10%

School of Engineering & Technology Vikram University, Ujjain 2012 – 2016 73.50%

Higher Secondary

Govt. Multi-Purpose H S Excellence School NO.1, Morena 2011 79.60%

SSC

City Montessori High School, Morena

2009 84.00%

ACADEMICS ACHIEVEMENT

Published paper entitled " Design of the Low Power Circuit with CMOS by using Adiabatic Technique"at 3rd International Conference on Electronics, Materials Engineering and Nano- Technology (IEMENTech 2019) will be organized by Electronics and Communication Engineering Department of IEM, Kolkata, India.

https://ieeexplore.ieee.org/document/8981316

ACADEMICS PROJECT

LANGUAGES

English

Full Professional Proficiency

Hindi

Full Professional Proficiency

OTHER

Design of Low Power Multiplexer circuit with CMOS Logic using adiabatic technique. (M.Tech)

EDA Tools: Cadence Virtuoso. Schematic

Capture:VirtuosoSchematic. Physical

Layout: Virtuoso.

Verification: DRC, LVS, QRC.

Implementation of Low Power Multiplexer circuit with CMOS Logic using adiabatic technique. We have designed and simulate low- power with a high-speed CMOS circuit. RFID Based Automatic Toll Tax Collection. (B.E)

Electronic toll collection system allows the vehicle drivers to pass the toll tax booths without stopping at the toll booths. The toll amount is deducted from the RFID card.

Infra-Red transmitters used are IR LEDs. We are going to use a Microcontroller of 8051 family

Verification : DRC, LVS,

QRC

EDA Tools : Mentor

Graphics, ISE – Xilinx,

Cadence

Knowledge : RTL Coding,

FSM based design,

Simulation,

Hardware Description

Languages : Verilog,

VHDL, System Verilog

SAURAV DIXIT

Determined and result-oriented individual. Looking for an opportunity to utilize my skills to help the company and my future peers to grow.

Basic knowledge of C

, C++ Language

INTEREST&

STRENGTHS

WORKSHOP CERTIFICATION / TRAINING

Certificate for Recent Trends in VLSI Design.

Certificate for Analog IC Design - Circuit and Layout Design Methodology using Cadence Design Flow at D.A.V.V, Indore

DECLARATION

I hereby declare that the information contained herein is true and correct to the best of my knowledge and belief.

Date: Saurav Dixit

Zeal to learn new things,

Listening to music, Self-

disciplined, self-confident and

hard working

Contact this candidate