Design Engineering

KAJA NAGENDRA KUMAR

D.NO:**/**/**, Email: ********.*******@*****.***

Near Marvadi Temple Street, Mobile: +91-970*******

Canal Road,One Town,

Vijayawada, Andhra Pradesh

LinkedIn ID- https://www.linkedin.com/in/kaja-nagendra-6777a616a

Summary of Qualifications

Good understanding of the ASIC and FPGA design flow

Extensive experience in writing RTL models using Verilog HDL.

Good experience in writing Test benches using SystemVerilog and UVM

Very good knowledge in verification methodologies

Experience in using industry standard EDA tools for the front-end design and verification

VLSI Domain Skills

HDL : Verilog

HVL : SystemVerilog

Verification Methodology : Coverage Driven Verification, Assertion Based Verification

TB Methodology : UVM

Protocols : AMBA, AXI, SPI

EDA Tools : Riviera Pro – Aldec

ISE – Xilinx

Domain : ASIC/FPGA front-end Design and Verification

Knowledge : RTL Coding, FSM based design,

Simulation, Code Coverage,

Functional Coverage, Synthesis,

Static Timing Analysis, ABV- SVA

Professional Qualification

Advanced VLSI Design and Verification course from Maven Silicon VLSI Design and

Training Center, Bangalore

June 2018 – December 2018

Educational Qualification

Completed Bachelor of Technology in the stream of Electronics and Communication

Engineering from NRI Institute of Technology affiliatedi by JNTU Kakinada

With 65%.

Passed from Sri Chaitanya Junior College Vijayawada in 2014 with 76%

Passed from KCSR English Medium School Vijayawada in 2012 with 6.3 GPA

VLSI Projects

[1] AHB-APB -AMBA Bridge Protocol Bridge Protocol Design and Verification

HDL: Verilog

EDA tool: ISE-Xilinx

HVL: System Verilog

TB Methodology: UVM

Description: The AHB-APB is used mainly for the communication between High Clock

Frequency Peripherals and Low Clock Frequency Peripherals by a concept of pipelining. The

AHB to APB Bridge has its AHB interface connected to a master port on an AHB Channel

module, and its APB interface is connected to a slave port on an APB Channel module.

Responsibilities:

Architected the block level structure for the Bridge

Developed Verilog RTL for each block

Architected the class based verification environment in UVM

Verified the Protocol by connecting maters and slave back to back

Generated functional coverage for verification sign-off

Project Location-Bangalore,India

[2] AMBA AXI4 Protocol Verification

HVL: System Verilog

TB Methodology: UVM

EDA Tools: RivieraPro-Aldec

Description: The AMBA AXI Protocol is targeted at high-performance, high frequency system

and includes a number of features that make it suitable for a high-speed performance.

AXI Master is a configurable UVM based Verification IP. It verifies the AXI Protocol and

generates the required functional coverage.

Project Location-Bangalore,India

[3] SPI Controller Core - Verification

HVL: SystemVerilog

TB Methodology: UVM

EDA Tools: Riviera Pro - Aldec

Description: The SPI IP core provides serial communication capabilities with external device of

variable length of transfer word. This core can be configured to connect with 32 slaves.

Responsibilities:

Architected the class based verification environment in UVM

Defined Verification Plan

Verified the RTL module using SystemVerilog

Generated functional and code coverage for the RTL verification sign-off

Architected the block level structure for the Bridge

Project Location-Bangalore,India

Curriculum Project

Router 1x3 – RTL design and Verification

HDL: Verilog

HVL: SystemVerilog

TB Methodology: UVM

EDA Tools: Questasim and ISE

Description: ROUTER is a networking device that forwards data packets between computer

networks. It drives an incoming packet to an output channel based on the address field contained

in the packet header.

Responsibilities:

Architected the block level structure for the design

Implemented RTL using Verilog HDL.

Architected the class based verification environment using SystemVerilog

Verified the RTL model using SystemVerilog.

Generated functional and code coverage for the RTL verification sign-off

Synthesized the design.

Project Location-Bangalore,India

Engineering Project

Project Name: RF Based Speed Monitoring and Anti-Collision System for automobile

Tool : Arduino UNO

Place: Bangalore

KAJA NAGENDRA KUMAR

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