Electrical Engineer Design

NARLA PAVAN SAI PRASAD

E L E C T R I C A L E NGINEER

P +1-937-***-**** E

narla.chinnu.999@gmai

l.com

A Springfield, OH W

https://www.linkedin.co

m/in/pavan-sai-prasad-

narla-42595219b

PROFILE

KEY SKILLS

Innovative and energetic Electrical Engineer with exceptional technical skills in circuit design. Seeking a challenging career in semiconductor industry which provides room to actualize my potential while fulfilling the organization goals.

Tools: Xilinx Ise, Vivado, Quartus

Prime, Cadence Virtuoso,

Synopsys Tetramax, Modelsim,

Simulink, Matlab, RSLogix 5000,

LogixPro, Microwind, HFSS,

Arduino, Oracle Applications,

Hardware: Zed Board Zync

Development & Evaluation Kit, NI

MyDAQ, Arduino Uno, Altera Max

Cyclone Iv Deo Nano ADC

Programming Languages

(HW/SW): Verilog, System

Verilog, VHDL, Python, Microsoft

Office, C, C++, Java, SQL,

PLSQL.

Other: Fault Analysis, Fault

Minimization, PODEM, SCOAP

Testability Analysis, RTL Scan,

LBIST Test Generation & Output

Analysis, Boundary Scan,

Combinational and Sequential

Circuit Design Using FPGA, Do

File Generation, ASIC Design

Spoken Languages: English,

Telugu, Hindi.

EDUCATION

Master of Science in Electrical Engineering (Jan 2019–Present) Wright State University, Dayton, OH GPA – 3.85

Related Coursework – Digital Integrated Circuit Design, Industrial Controls & Automation, Low Power VLSI Design, Embedded Systems, VLSI Testing and Design for Testability

Bachelor of Technology in Electronics & Communication Engineering (July 2014-May 2018)

Koneru Lakshmaiah University, Vijayawada, India GPA – 3.5 Related Coursework – Control Systems, Electronic Devices and Circuits, VLSI Design, Digital System Design, Design for Testability. ACADEMIC PROJECTS

Verilog implementation of Reduction Approach for power droops during Launch on Shift Scan Based Logic BIST April 2017 Applied the Low Power and High Reduction approach to reduce the power droops. The approaches are designed by Verilog HDL and simulated by Modelsim. Designed and customized in order to enable the scalable Power Droop reduction at the capture of up to 87%. Future scope is it can be implemented in hardware Xilinx tool FPGA Spartan 3XCS3S

Comparative Analysis of 6T, 9T and 13T SRAM Cells May 2018 Applied clamping diode technique to the SRAM and found the power dissipation. Designed the circuits in tanner tools and compared the power dissipation of the 3 SRAM cells. Designed the layouts using Microwind and found the layout level power dissipation of the SRAM cells

Implementation of Drip Irrigation System using PLC April 2019 Designed a flowchart for the process flow of the system. Used the tools LogixPro and RSLogix 5000 to design the Ladder Logic. Learnt about the working of the moisture sensor and used it in the design. Monitored the performance of the design using the timing diagram Design and analysis of 6 Stage Pipeline Adder using VHDL and Virtuoso November 2019

Used Vivado and Cadence Virtuoso tool for the design and simulation. The delay of 6 clock cycles is verified for the 6 stage. The main objective of this design is all the inputs reach the certain subsystem at the same time. We have used the 28T adder using inversion property adder in order to reduce the power dissipated at the transistor level. Design and analysis of 7x7 Booth Multiplier using VHDL and Virtuoso May 2020

Used Vivado tool for the digital design and simulation. The schematic level of the multiplier is designed using Cadence Virtuoso. The main use of this design is to design a multiplier which results in faster feedback and response. We made the use of 28T adder using inversion property as an adder and a linear feedback shift register in order to reduce the power dissipated at the transistor level. EXPERIENCE

Associate Consultant

Wipro Ltd, Bengaluru, India

May 2018-Dec 2018

Practical experience in the field of

IT. Creation and updating of

database for clients to maintain the

privacy of data. Studied how data of

the database is sorted and stored

internally in real time. Creation of

different lists, menus and options

using Oracle Applications Server

tool.

EXTRA CURRICULAR

• Honored with Certificate of merit in ELAT in English conducted by Colorado University.

• Worked as organizer for Android Java workshop conducted by Indian Institute of Technology, Roorkee.

• Organized Paper Presentation Event in Technical Fest Samyak 2016 at KL University India.

• Worked as a volunteer for National Service Scheme India.

• Awarded with Certificate of Merit in Robotics Championship conducted by Indian Institute of Technology, Bhubaneswar.

• Honored with Certificate of Excellence in PCB Design Championship Conducted by Indian Institute of Technology, Bhubaneswar.

PAVAN SAI PRASAD NARLA

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