YESUKUMARA R K

Email:adhwjs@r.postjobfree.com

Cell no:+91-938*******. Bangalore, Karnataka

VLSI Domain Analog and Mixed Signal

EXECUTIVE SUMMARY

o A dedicational professional with 3 Years of Experience. o Good experience in layout design and verification using Cadence in Analog and custom digital. o Full custom and semi-custom layout design using Cadence tool. o Competent to work in highly diverse environment with people from varied backgrounds. PRESENT WORK EXPERIENCE

Company. : Arise techno solutions.

Designation. : Design Engineer.

Experience. : Sep 2017 to till Date.

RESPONSIBILIES

Model layout work involves area estimation, Floor planning, Define port location for sub modules, Power grid /mesh planning, Signal route planning, Schedule planning, Block level integration and Top level integration.

Quality Checks involving DRC, LVS, DFM, CC Extraction, Antenna, EM, IR, ESD and Latch-up

Sign off work involves changing certain sub modules of the chip for performance issues; It can also have Alteration of floor plan of existing layout. Sometime we would have to modify routings to meet parasitic constraints.

Delivering high quality layout that satisfies to all design requirements.

Participate in layout reviews across various teams.

Interact with circuit designer for overall layout development and improvement.

Encouraging team players to get better Layout Quality within scheduled time slot.

Layout design & Layout review documentation if required.

Preparing Current & Resistance Calculation table for metal with the help of design Rule Manual

(DRM)

TECHNICAL EXPOSUR

Technology nodes: TSMC 7nm, TSMC 28 nm, FDSOI P28nm, TSMC 40nm, TSMC 65nm, TSMC 90nm, BCD8SP 160nm.

Tools : Cadence Virtuoso (EDA Tools)

Layout editor : Cadence Virtuoso (L,XL,GXL)

Layout verification: CALIBRE Verification, ASSURA Verification. PROJECTS HANDELED

Project : Two stage OTA and level shifter layout design (TSMC 7nm FINFET) Description : Two stage OTA block is having first stage differential Amplifier and second stage common source Amplifier, Resistance ladder Network, bipolar device and main Current mirror.

Responsibilities : Floor-plan, Placement and matching, Routing Layout, DRC, LVS. Tools : Cadence – DFII, Virtuoso Cadence Virtuoso Layout editor and CALIBRE Project : I2C (BCD8SP 160nm)

Description : The top level I2C consists of a Schmitt, Filter, and Driver, Pre driver, ESD Res and control logic. One end of circuit is connected to IO PAD, and all this blocks are implemented within Deep N well. The complete I2C macro measured 150um 215.4um

Responsibilities : Floor-plan, Placement and Routing Layout, DRC, LVS, DFM, Deep N well and Antenna diode insertion, parasitic diode area into schematics for area match in LVS.

Tools : Cadence – DFII, Virtuoso Cadence Virtuoso Layout editor, CALIBRE for DRC, DFM

& LVS for Verification

Challenges faced : Driver one end is directly connected to IO PAD, Routing of this according to current values and Deep N well insertion.

Project : Generic IO Library (Fujitsu 28nm)

Description : Various generic IO’s such as Supply, Ground, Core-clamps and Bidirectional IO’s with 4 & 8 mA current drives in standard frame size of 180X50 were laid-out. Also cells like Corner & various width filler cells & cut cell were laid-out. Bidirectional pads: PRDW0204SCDG, PRDW0208SCDG, Supply pads: PVDD2AC, PVDD3AC Ground pads: PVSS1CDG, PVSS2CDG

Responsibilities : Floor-plan, Placement and Routing Layout, DRC, LVS Tools : Cadence – DFII, Virtuoso Cadence Virtuoso Layout editor, CALIBRE for DRC & LVS for Verification.

Project : DCDC (P28, FD_SOI)

Description : This consists mainly comparators (VCR), Clock control, Control logic, Low current, High current switching logic with multiple number of instances, an input voltage ranging from 1.8 to 5.5v.

Responsibilities : Floor-plan, Placement and matching, Routing Layout, DRC, LVS. Tools : Cadence – DFII, Virtuoso Cadence Virtuoso Layout editor, CALIBRE for DRC & LVS for Verification.

Challenges faced : Clock signal routing without coupling with other gate signals and differential matching in comparator

Project : PCI Gen 2, 8.5Gbps PHY – ABIST_TOP (TSMC 28nm) Description : The Top level of this SerDes PHY consists of a TX, CM and RX block with 5 X 3 C4 pads at 180 um pitch. The complete SerDes PHY macro measured 890 X 514 um. Layout of complete Analog Built In System Test (ABIST_TOP) block measuring 120 X 420 um consisting cells like ABIST_VREF, ABIST_IREF, ABIST_INPUT_LVL_SHFT, ABIST_INPUT_HYSTCOMP.

Responsibilities : Floor plan, Placement and Routing Layout, DRC, LVS, Shielding & Decoupling cap insertion, Dummy fill.

Tools : Cadence – DFII, Virtuoso, Cadence virtuoso layout editor, Calibre for Verification Challenges faced : The ABIST block was a replacement for Digital BIST and hence there was severe limitation on the form factor of the cell, it had to fit in 120 X 420 um area at the top level.

Project : 8mA 1.0 V LDO REGULATOR for VBUS (USB2.0) (TSMC28nm) Description : The top level (USB2_VREG) is a 8mA 1.0 V regulator consists of cells like USB2_BANDGAP, USB2_OTA, USB2_RESDIV, USB2_ESDPMOS and USB2_VREG (TOP)

Responsibilities :Understanding of ESD hardening and Latch-up rules for PMOS, Layout of ESD hardened PMOS, Layout of cells like USB2_BANDGAP, USB2_OTA, USB2_RESDIV, USB2_ESDPMOS & USB2_VREG(Top level)

Tools : Cadence – DFII Virtuoso, Cadence virtuoso layout editor, CALIBRE for Verification Challenges faced : The output of LDO was driving the IO Pads directly and hence the PMOS pass transistor had to be ESD hardened following ESD rules. Project : Band-Gap Reference for BT2.0 in (TSMC 90nm) Description : BJT less Band-gap: This Band-gap is a MOS based sub-threshold design in TSMC 65nm. This block measures 400 X120 um and is introduced in DNW for low noise. Responsibilities : Floor plan, Placement and Routing Layout. DRC, LVS, Shielding & DNW insertion, Dummy fill.

Tools : Cadence – DFII Virtuoso, Cadence virtuoso layout editor, Calibre for Verification Challenges faced : Back annotation of parasitic diode area into schematics for area match in LVS in ASSURA flow.

TECHNICAL EXPERTISE (SKILLS)

• Good understanding of CMOS fundamentals and fabrication process, Analog technique to implement critical device matching and signal balancing Techniques

• Standard Analog layout techniques and good understanding of physical and electrical aspects of layout..

• Familiar with Deep n-well, Reliability issues like EM, IR Drop, Antenna effect and latch-up and how to overcome those issues.

• Layout techniques to overcome parasitic issues for high speed signals.

• Key layout techniques to overcome issues/error due N-well proximity effect and shallow trench Isolation effect and LOD effect for high speed. ACADEMICS

Master of Technology (M.Tech) in Digital electronics with first class from SJB institute of Technology Bangalore, Karnataka, India. (2015-2017)

Bachelor of engineer(BE) in electronics and communication from vishweshwariah technological University, Karnataka, India. (2015)

PERSONA DETAILS

Name : Yesukumara R K

Father’s Name : Kempegowda R K

Address : Ramanahalli village thendekere post K R pet Tq, Mandya Dist Karnataka- 571426

Date of birth : 06-04-1992

Sex : Male

Marital status : Single

Nationality : Indian

Languages : Kannada, English, Hindi, Telugu

DECLARATION

I hereby assure that, the information furnished above is true to the best of my knowledge and belief.

Place: Bangalore (YESUKUMARA R K)

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