Design Engineer Power

Kapil Nagdive

Mobile: +91-865*******

Email: ************@*****.***

Passport No: P9276617

RTL design engineer with experience in SoC Integration. Experties in RTL coding, RTL debugging, bug fixing. Worked on SoC and IP Integration/Development, ASIC low power design techniques. Good exposure in architecting and developing RTL.

Work Experience:

Total 14 years experience.

Currently working with L&T Technology Services, Pune from 9th April 2018 to till date.

Worked with Wipro Technologies, Hyderabad from 6th September 2017 to 6th April 2018.

Worked with Tata Power SED, Mumbai from 15th April 2013 to 31st August 2017.

Worked with ID Technologies, Pune from 23rd July 2007 to 6th April 2013.

Worked with Silicon Magic Tech Pvt Ltd, Pune from 18th April 2006 to 20th July 2007.

Technical Experties:

HDL Languages : Verilog, VHDL

RTL Entry & Synthesis Tool : Synopsys Design Compiler, Cadence RTL

Compiler.

Frontend EDA Tools : SpyGlass LINT, SpyGlass CDC, Questa CDC,

Synopsys Formality, Synopsys Prime Time.

Backend Tool : Synopsys StarRC.

Debugging Tool : Chipscope pro, Insert, Oscilloscope.

Simulation Tool : Model Sim 6.3f SE, Active HDL.

Schematic Entry : ORCAD 9.1.

Software Configuration management Tool: Git, ClearCase, Cliosoft SOS.

Other Programming Languages : Basic C.

Scripting Language : Tcl, Perl.

Operating Systems : Linux, Windows 9X, NT,2000, XP.

Key Competencies & Skills:

Experienced in SoC Integration.

Experience AXI protocol.

Proficent in RTL coding using Verilog & VHDL.

Worked on Spyglass-LINT, Spyglass-CDC.

Understanding of ASIC low power design techniques and UPF creation.

Worked on Synopsys based RTL2GDSII Flow.

Worked on Synthesis, LEC, STA, Extraction, Eco of LTE IP.

IP development with IBM CoreConnect Bus protocol for SOC application and embedded systems using 32 RISC processor Xilinx Microblaze.

Worked on PCIe bus based design implementation.

Worked on Validation of HDMI 2.1 Transrecevier Chip.

Experienced on FPGAs from Xilinx, Lattice and Altera Vendors.

Worked on standard buses like I2C & SPI.

Project Undertaken In LTTS:

CLOVER FALLS SoC (Client: Intel)

The Clover Falls (CVF) is a low power SoC with innovative computer vision applcations. Part of the CVF Design Team. Owned Integration, RTL QA of Host Peri and SMEM partions.

Tools Used: Synopsys Spyglass LINT, Synopsys Spyglass CDC.

Responsibility:

Responsible for Integrating/RTL coding multiple IP Drops of the partions owned.

RTL QA of the partions owned, Develop Constraints files for the partions owned.

MIPI DPHY IP

Responsible for implementing features like 16-bit interface and 8b9b Encoding for TX Block of DPHY IP. Worked on Lint, CDC flow for Tx Block of DPHY IP.

Tools Used: Synopsys Spyglass, Questa CDC, Cadence RTL Compiler.

Responsibility:

Responsible for modifying the RTL to implement 16-bit interface and implemented 8b9b Encoding block for Tx Block of DPHY IP.

Worked on Lint, CDC for Tx Block of DPHY IP.

IBIS19 (Client: Intel)

Responsible for Synthesis and LEC of IRX Block of LTE IP. Worked on Extraction flow, STA, ssssof LTE Top Block.

Tools Used: Synopsys Design Compiler, Synopsys Formality, Synopsys Prime Time, Synopsys StarRC.

Responsibility:

Responsible for Synthesis and LEC of IRX block of LTE IP.

Worked on Extraction, STA of LTE Top.

Project Undertaken In Wipro Technologies:

Validation of HDMI 2.1 Transreceiver Chip

Responsible for validating the design which supports HDMI specification 2.1, 2.0 & 1.4.

Tools Used: Xilinx Vivado, ChipscopePro.

Responsibility:

Responsible for making ASIC RTL compatible to FPGA.

Onchip Debugging using ChipscopePro.

Project Undertaken In Tata Power SED:

PCIe based Radar Video Acquisition Card

Responsible for designing, testing and deployment of PCIe x1 Gen 1 based 2 channel Radar video aquisitation card. The system is designed using Xilinx Spartan-6 LXT FPGA. Video signal is conditioned and digitized at high speed ADC. The digitized video is DMA transferred to host system software for displaying.

Tools Used: Xilinx ISE 14.2, ModelSim 6.6b.

Responsibility:

Developed RTL code for RCP compression, Video Framer, Header Framer.

Implemented BMD design for data transfer.

Elecronics for Uncooled Thermal Sites

Spartan-6 FPGA is used for capturing frames form Uncooled Thermal Detector via Camera-Link, Storing captured frames in 8 different SRAMs. Perform NUC (Non-Uniformity Correction) algorithm on the captured frame for calibrating the detector and storing the result in FLASH.

Tools Used: Xilinx ISE 14.2, ModelSim 6.6b.

Responsibility:

Developed RTL for capturing frames from Uncooled Detector via Camera-Link.

Developed RTL for reading/writing into 8 different SRAMs.

Developed RTL for reading/writing into FLASH.

Interfaced all the above IPs with Microblaze soft processor using Xilinx EDK.

Involved in firmware development in C for Microblaze processor.

Project Undertaken In ID Technologies:

Thermal Inkjet Barcoding Printer

Worked on developing industrial standard thermal inkjet printer which uses HP Inkjet printhead, Lattice XP2 FPGA and Atmel ARM9 processor.

Tools Used: Lattice Diamond 1.3, Synplify Pro, Active HDL.

Responsibility:

Developed RTL code to map buffered image on even and odd nozzles of TIJ printhead

Implemented TIJ specific serial protocol to communicate between host system and the

ASIC on the TIJ printhead.

Xilinx to Lattice porting

Logic porting from Xilinx to Lattice.

Tools Used: Lattice Diamond 1.2, Synplify Pro, Active HDL

Responsibility:

Made Xilinx RTL compatible with Lattice FPGA by making changes in different FIFOs and RAMs.

Added different functionality to the design and did hardware debugging till the point where the entire design became stable on lattice platform.

Thermal Transfer Barcoding Printer

Industrial standard High Speed Thermal Transfer Barcoding Printer which uses RHOM thermal printhead, Xilinx FPGA and Atmel ARM9 processor.

Tools Used: Xilinx ISE 10.1, ModelSim 6.3f SE.

Responsibility:

Developed RTL code for DES 64 bit decryption engine.

Developed RTL code for rasterizing buffered image and printhead specific serial protocol for sending the image to the thermal printhed.

Developed RTL code for a control engine to control various actions of printer such as feed, slew, print, forefeed, backfeed etc. This is a command based architechture.

Developed RTL code for interrupt control engine based on Intel 8259 architecture.

Developed RTL code for stepper motor controller which accelerate deaccelerate intelligently with programmable stepping mode.

Implemented SPI protocol to communicate with the ADC.

Implemented I2C protocol to communicate with the RTC and PSoC.

Project Undertaken In Silicon Magic Tech Pvt Ltd:

FPGA Development Board

Designing FPGA development board with XILINX Spartan-3 FPGA with peripherals such as ADC, LCD, RTC, RS232 etc.

Tools Used: Xilinx ISE 8.1, Modelsim 6.0a, Orcad 9.1.

Responsibility:

Schematic design of FPGA board.

Implemented RTL code to interface peripherals such as ADC, LCD, RTC etc.

Served as a Lab Instructor in MKCL

Company provided technical resources for VLSI training program under MKCL.

Responsibility:

Guiding student in their Lab assignments and projects.

Trainings Undergone:

Post graduate diploma in VLSI Design in the year 2005 from ICIT, Pune University, India

Academic Profile:

Master Degree in Electronics (M.Sc) in the year 2004 from DECS, Campus, Nagpur, under Nagpur University.

Bachelor Degree in Electronics (B.Sc) in the year 2002 from Institute of science, Nagpur, under Nagpur University.

Higher Secondary School Examination (HSC) in the year 1999 from Dr. Babasaheb Ambedkar Jr. College, Nagpur.

Secondary School Examination (SSC) in the year 1995 from C. P. & Berar High school, Nagpur.

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