Engineer Design

Saritha Satti

* ***. *********** **** ********

**** ** **** **** ***# 2103, Mob : 262-***-****

West Des Moines, IA 50266 E-mail: *****.*******@*****.***

Career Objective

Having a thorough knowledge on FPGA based design flow, implementation, simulation, STA and troubleshooting the flaws in the design. I am looking for a challenging position wherein I can be a part of latest technologies and work on designing on FPGA so I can use my expertise which would benefit the company and my career.

VISA status: H4-EAD Valid till 11/22/2020

Employment Summary

As a Sr. FPGA design Engineer at Ineda Systems(Acqui-hired by Intel in 2019) from Aug'2013 to Dec'2014

As a Product Applications Engineer at Xilinx from May’2007 to Jan’2012

As a Customer Applications Engineer at CMC from June'2006 to April'2007

Education

Post Graduate Diploma in VLSI Design from Sandeepani School of VLSI Design, Hyderabad, India in the year 2006.

Bachelors (B.Tech) in Electronics & Communications from VNR Vignana Jyothi Institute of technology (Affiliated to JNTU), Hyderabad, India in the year 2004.

Intermediate from Vignan Vidyalayam, Hyderabad, India in the year 2000.

10th standard BHEL Higher Secondary, B.H.E.L, Hyderabad, India in the year 1998.

Skills

Languages: Verilog HDL, VHDL, System Verilog

Scripting: Tcl, Perl.

Simulators: Modelsim SE, Questa 10.0, ISIM (Xilinx simulator)

Tools: Xilinx Vivado, Xilinx ISE, Timing Analyzer, Synplify Pro, EDK, Chipscope ILA, Altera Quartus, SignalTap II Logic Analyzer, Palladium ICE tool (basic flow), Vi Editor, CVS.

Protocols: AXI, PLB, I2C, SPI

FPGAs: Virtex-4/Virtex-5/Virtex-6, Spartan-3/Spartan-3E/Spartan-6, Stratix V

OS: Linux and Windows.

Professional Experience

Worked as Sr. FPGA design Engineer in Ineda Systems, Hyderabad from 26th Aug 2013 to 12th Dec 2014.

oInvolved in pre-silicon ASIC Validation using FPGAs like Stratix V.

oInvolved in porting the clocks modules up to the FPGA and pin assignments.

oInvolved in solving the design issues while running the design in Altera Quartus.

oInvolved in solving the timing violations at various stages of design flow in Altera Quartus.

oInvolved in simulation to check the basic functionality of the design.

Worked as Product Applications Engineer in Xilinx, Hyderabad from 1st May 2007 to 27th Jan 2012.

oInvolved in implementing and verifying the functionality of multimedia accelerator on SoC (using EDK and SDK tools as a mini project).

oInvolved in providing design assistance and support on Xilinx ISE - Synthesis, implementation, floorplanning and PlanAhead, ISE simulators to the customers from North America, APAC, Indian customers. Provided guidance on the FPGA device architecture to the customer and guide them to design

oDebugged complex designs for synthesis and implementation issues with detailed knowledge of digital design and extensive knowledge on the Synthesis and Implementation tools.

oContributed to a good number of internal answer records on the known issues/design advisories.

oWorked closely with R&D to meet the customer requirement on tool enhancements and issues.

oInvolved in testing the new releases and reviewing the documentation.

oInvolved in assisting customers on Xilinx tools installation and licensing.

oDeliver trainings on Xilinx tools to customers, and Xilinx employees that covers hardware structure, software features, and best design practices by maintaining a high level of customer satisfaction.

oDelivered trainings on PlanAhead with Virtex-5 architecture to Ineda Systems

oDelivered WebEx training sessions on PlanAhead design flow to Qualcomm, Bangalore.

Worked as Customer Applications Engineer at CMC, Hyderabad from 19th June 2006 to 30th April 2007

oInitially Xilinx was partnered with CMC Limited to develop leading-edge FPGA technology solutions. Later in 2006 Xilinx established as a self-governing company. Xilinx management was pleased with my work and acquire.

oInvolved in providing design assistance and support on Xilinx ISE - Synthesis, implementation, floorplanning and PlanAhead, ISE simulators to the customers from North America, APAC, Indian customers. Provided guidance on the FPGA device architecture to the customer and guide them to design

oInvolved in assisting customers on Xilinx tools installation and licensing.

Recognitions

Received appreciation letter from VNR VJIET HoD - for introducing System Verilog language at the AICTE Sponsored Faculty Development Program on VLSI Design

Nominated as Team Player – 2010, World Wide team in Xilinx

Received certificate from customer – Support aiding to sales in Xilinx

Certified online for completion of “SOC Verification using System Verilog” from Udemy

Strengths

1)Ability to communicate technical information in an organized and understandable fashion, excellent interpersonal, telephone, and written communication skills with a confident presence.

2)Good organizational skills with the ability to multitask, prioritize, and track activities, problem solving skills and creative interactive approaches to tackling problems

3)Pro-active in taking up challenging tasks and meeting the deadlines.

Projects Summary

Verification environment in System Verilog for I2C:

Description: I2C defines the architecture, signal interface, register interface and parameterized options I2C bus interface module and provides low-speed two-wire serial bus interface to popular devices

Client: Worked for a startup.

Role: Developed verification IP in SV for testing the I2C bus interface.

Written testcases for SPI Verification IP:

Description: Serial Peripheral Interface Bus or SPI bus operates in full duplex mode and devices communicate in master/slave mode where the master device initiates the data frame. Multiple slave devices are allowed with individual slave select lines and SPI is called as four-wire serial bus

Client: Worked for a startup.

Role: Developed testcases for SPI bus interface.

Course Work Project at Sandeepani:

Design of Digital Alarm Clock

Role:

1)Designed a Digital Alarm Clock using Verilog, which can display Current time, load new time, set alarm time, sound alarm.

2)Test benches are written for all the modules and the top-level module and functionally verified using Modelsim.

Knockout ATM Switch

Role: Designed Knockout ATM switch using VHDL which has three layers Packet Filter, Concentrator and Packet Buffer.

Academic Project - B.Tech:

Ethernet Based Access Control System

Role:

1)Developed Schematics Diagrams and Coding for Ethernet Based Access Control System is an application by which we can control and register the entry of a person into the campus

2)The code is written to initialize the components and using AVR GCC tools; the controller is activated and utilizes all the interfaces for its application

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