NIKITHA.R
Email : adh4ad@r.postjobfree.com
Mobile : 967-***-****
CAREER OBJECTIVE:
Looking forward for a bright career in a leading organization to apply and enhance my technical skills with a practical touch where I can contribute for the growth and betterment of organization with best of my abilities.
HAVE WORKED ON TOOLS :
1. QFLOW :
• Physical verification of standard cell layout using QFLOW which includes Synthesis, Placement
&Routing, Static Timing Analysis, GDSII and also checks like DRC, LVS and Physical Verification.
• Performing circuit extraction procedure on the finished layout to determine parasitic capacitances and netlist, Dynamic Power Consumption and resistances using Qflow tool.
• Analysing standard cell schematics using technologies like 18nm,35nm,45nm,50nm.
• Worked on Yosys, Graywolf, Qrouter, Magic which is used for Synthesis, Placement, Routing, layout .
• Analysing of Netlist for optimization.
2. CYMPLEX TOOL :
• Analyses of Behavioral Design, Structural Design.
• Logic Design Netlist to be Analysed.
3. MODELSIM :
• Verification using System Verilog.
4. XILINX :
• FPGA Design and Implementation.
5. ELECTRIC TOOL :
• Using of LTspice .
• Analysing of both Analog Design and Digital Design.
SYNOPSYS VCS :
• Performing lint-checks.
• Inserting assertion checks.
• Analyses of coverage points.
• Verifies using System Verilog .
• Obeserved simulation using waveforms through ICARUS VERILOG. ACADEMICS:
Qualification
Institution
Board/University
Year
Percentage/
CGPA
B.E. Er.Perumal Manimekalai
College of Engineering
Anna
University
2015-19 7.99
PUC
Jyoti Nivas Pre University
College
PU Board 2015 60.17
(PCMB)
SSC Bethel Matriculation
school
State Board 2013 91.4
PROJECTS:
SPI Protocol
• Implemented using Modelsim.
• The Serial Peripheral Interface is a Synchronous Serial Communication Interface specification used for short-distance Communication.
• It provides full duplex communication at very high frequency written with Verilog code and also using System Verilog .
• Also, Verified using Synopsis Vcs.
• Analysed Lint-checks, Coverage and Assertions.
UART Protocol
• Implemented using Modelsim.
• Written System Verilog and respective testbench.
• Universal Asynchronous Receiver/Transmitter use serial data and it communicate directly with each other.
• Also, Verified using Synopsis Vcs.
• Analysed Lint-checks, Coverage and Assertions.
I2C Protocol
• Implemented using Modelsim.
• Written System Verilog and observed it’s characteristics.
• It is a serial communication protocol so data transferred bit by bit. FIR Filter
• Designed using FDA Tool in matlab and implemented using QFLOW and XILINX ISE.
• Written Verilog code and test bench.
• Verified using Synopsys vcs.
• Analysed lint-checks and assertions .
• Simulated using Icarus Verilog .
Analysing Encoding Data for Dynamic Power Consumption
• Written Verilog code and test bench for 8 bit, 16 bit and 32 bit.
• Studied ASIC flow design using various tools offered by Qflow which includes RTL design to gdsii and generation of netlist is observed. Also learned floor-planning, place and route for thedesign.
• Analysed Layout design.
SAR-DAC
• Designed SAR-DAC as per the given specifications in Electric Tool and observed its transfer characteristics.
N-Bit Multiplication
• Implemented using QFLOW .
• Designed from RTL to GDSII and Analysed Layout using a tool MAGIC.
• Written Verilog code and its testbench to analyse waveform using a tool IVerilog. WORKSHOP:
Workshops held on
• CYMPLEX TOOL – Synthesis, Logic Circuit held @ PMC TECH. SKILL SET:
Languages : Verilog, System Verilog, Python, Matlab, C EDA Tools : Qflow, Cymplex tool, Xilinx-ISE, Electric, X-HDL, Tanner TSpice, Icarus Verilog, Verilator, ModelSim.
EXPERIENCE:
ORGANISATION : SANARYS PVT LTD
DESIGNATION : ASIC PHYSICAL DESIGN
DURATION : SEPTEMBER 2019 TO OCTOBER 2020
RESPONSIBILITY : WORKED ON QFLOW, MODELSIM, XILINX, ELECTRIC, LTSPICE, CYMPLEX TOOL, SYNOPSIS VCS, ICARUS VERILOG.
EXPERIENCE:
DR. CYRIL PRASANNA RAJ P
HEAD & DEAN R&D
M.S ENGINEERING COLLEGE
Email: adh4ad@r.postjobfree.com
Nikitha.R