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Engineer Engineering

Location:
Vasant Nagar, Karnataka, India
Posted:
November 22, 2020

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Resume:

B. VISHNU VARDHAN

EMAIL : adh1xg@r.postjobfree.com

Phone number : 918-***-****

Objective

To secure a challenging position where I can effectively contribute my skills as DFT professional. Skills & Abilities

TECHNICAL SUMMARY

Worked on Scan insertions ATPG generation

Worked on post & pre dft drc analysis & fixing

Full scan/Compression analysis & implementation

ATPG for stuck at & Transition delay fault models and coverage analysis

JTAG & Boundary Scan knowledge

Basic knowledge in RTL flow

PROFESSIONAL EXPERIENCE

[VLSI GURU ] June 2019 to Present [DFT engineer - Trainee] SKILL SETS

Simulation Tools : Synopsys VCS, Modelsim, DFT Advisor, Test Kompress, DC_SHELL

Operating Systems : Linux, Windows

Programming Language: basics of C

HDL: Verilog

Microsoft word

Microsoft PowerPoint

WORK EXPERIENCE:

[VLSI GURU]:

[DFT Engineer - Trainee]

Ongoing Project: [TEST-1]

Description: Pattern generation & DRC analysis at block level. Flop count: 80k Responsibilities:

DRC Analysis & fixing

Pattern generation for both stuck at & TDF models PROJECT 1: [TEST 2]

Description: Partition level pre_dft & post_dft DRC checking, Scan chain DRC checks & fixing & generating the patterns. Flop count: 40.3k

Responsibilities:

Block level pattern generation

Scan chain violations checks

Pre & Post DRC analysis & fixing. (scan insertion violations) Page 2

Project 2: [TEST 3]

Description: Partition level scan ability checks, Scan chain DRC checks & fixing & generating the patterns & inserted edt logic. Flop count : 63k

Responsibilities:

Block level pattern generation

Scan chain violations checks.

Pre & Post DRC analysis & fixing. (scan insertion violations)

Block level edt insertion.

STRENGTHS

Fast learning nature

Leadership Quality

Ability to work in a team

Mathematical ability

Reasoning skills

workaholic

INTRESTS

Playing Cricket, Chess

Puzzle solving

Education:

Bachelor of Technology, Electronics and Communication Engineering (2019), CGPA -7.6 Sree Vidyanikethan Engineering College, A.Rangampet, Andhra Pradesh

Board of Intermediate, M.P.C (2015), Percentage – 97.6 Sri Chaitanya junior College, Vijayawada, Andhra Pradesh

Secondary School Certificate (2013), CGPA – 8.7

Sri Imam Shareef(E.M) High School, Andhra Pradesh

PERSONAL DETAILS

DATE OF BIRTH : 4 February, 1998

NATIONALITY : Indian

GENDER : Male

PERMANENT ADDRESS : D.No:4-78A, Old town, Mudigubba, Anantapur district LANGUAGES KNOWN : English, Telugu

DECLARATION

I here by declare that the information given above is true to the best of my knowledge. DATE : Signature

Place : B. Vishnu Vardhan



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