Damireddy Geeta Priyanka Reddy

+1-513-***-****, Cincinnati, OH, USA. adgyzc@r.postjobfree.com

Personal mail: adgyzc@r.postjobfree.com LinkedIn: www.linkedin.com/in/geetapriyankareddydamireddy/ EDUCATION

Master of Science: Computer Engineering Expected July 2021 University of Cincinnati, Cincinnati, OH GPA: 3.4/4 Honors: Recipient of University Graduate Scholarship (UGS) Completed Courses: Introduction to VLSI Design, Advance Algorithms, Embedded Systems, VLSI Design Automation, VLSI Design for Test and Low Power, Topics in VLSI/CAD, Trust in digital Hardware, Chip Designing and testing, DFT, Basic STA concepts. Bachelor of Technology: Electronics and Communication Engineering Jun 2015 - Jan 2019 SASTRA University, Thanjavur, TN, India GPA: 8.1/10 EXPERIENCE

SoC Design Engineer - DFT intern at Intel Corporations, Santa Clara, CA, USA (TCL) June 2020-Nov 2020

• Worked with SoC Design team, dealing with scan chain insertion of an RTL design and gate level Netlist.

• Implementing DFT design for the IO macros using a tessent tool (Mentor Graphics).

• Verification by using VCS tool, Synthesis of RTL design. FPGA based embedded Hardware trust application - Student Intern at UC, OH, USA (Python, C++) Jan 2019-jun 2019

• Performed operations on FPGA based Hardware security and SAT attack application on Trust hub benchmarks.

• Extracted keys from all the benchmarks by using python script and tested it with the generated keys using FPGA board.

• Interacted PC with Nexys 4 DDR board (FPGA), usage of UART serial communication which integrates the ISCAS’85 benchmarks and the most known schemes are susceptible to the Boolean Satisfiability (SAT) based Attacks.

TECHNICAL SKILLS

Physical Design, ASIC Design, DFT, RTL Design and simulation, FPGA.

• Programming and Scripting Languages: C, C++, Python, Tcl, Perl, Shell scripting, MATLAB

• Operating systems Linux/Unix, Windows

• Version Control: Git

• Hardware Description Language: Verilog, VHDL, System Verilog

• Hardware boards and Architectures: Nexys 4 DDR FPGA, Basys 3 FPGA, Altera II FPGA, 8086 Micro Processor, Atmega8 Micro Controller.

• Simulation Tools: Tessent tool, Synopsys Design Compiler, Vcs simulation tool, RTL synthesis, MAGIC Layout Editor, HSICE, IRSIM, Model Sim, Quartus II, LABVIEW, Tetra Max (ATPG patterns) PROJECTS

• Hardware Trojan detection by using Machine learning Algorithm (IEEE paper implementation)- Converted Verilog design to networkx Digraph. Extracted Trojan features for the (ISCAS’85 benchmarks). Used the extracted features and applied ML algorithm (SVM) to classify trojan nets and normal nets.

• Chip design for Cipher text- A chip is designed for Cipher text (an important issue in security). Implemented using Magic Tool which is a 70 bit-slice chip with an operating speed of 100 Mhz. The design was sent to MOSIS for fabrication using 0.3μm feature size.

• Design, Synthesis & Scan Chain Insertion - Designed a Fibonacci machine in RTL and translated to gate level netlist using Synopsis DC. Scan chains were inserted to improve testability. The synthesized design was tested for faults using Tetra Max.

• Partitioning using Simulated Annealing - Implemented the Simulated Annealing partitioning algorithm in C++. Tested the tool on netlist with 100 thousand cells and 1 million nets, under 10 minutes of CPU time.

• Placement and Routing - Implemented Force directed placement algorithm and Lee’s Maze routing algorithm in C++. Tested the design automation tool with netlist with 2k cells and 2knets.

• RSA cryptosystem- Implemented an RSA cryptosystem by encrypting a message (BEARCATII) to secure data.

• Gesture control servo motor -Designed a boat by using proximity sensor application and servomotor.

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