NARENDRA MANCHINEELLA Email : adgqex@r.postjobfree.com

Mixed Signal Layout Mobile: +91-720*******

OBJECTIVES

To excel in the field of Mixed signal Layout and to get recognized as an eminent engineer in the organization and contribute my best to the organizational success.

5 years of hands on experience in Finfet (5nm & 7nm), Analog Mixed Signal and standard cell Layout design in lower node processes.

Experienced in handling high speed Analog/Mixed Signal Layout Designs of various critical analog blocks such as Seders RX/TX(CMOSCLOCKS,CLK2_DIST),Dual Channel Spine(Dual Lane).

Experience in working with Cadence Virtuoso Layout editor, Virtuoso Schematic editor and proficient in custom analog/mixed-signal layout design, particularly in TSMC 5nm, 7nm.

Experienced in Half cell structured layouts for critical blocks to achieve better matching for input/output signals and Deep N-well to isolate substrate.

Hands on experience in handling high speed clock signals with side shielding and clock tree fashioned routing to overcome the timing delays.

Experienced in physical verification (Chip level), debugging skills like LVS/DRC/DFM/Antenna and other layout issues.

Currently working as Mixed Signal Engineer for ACIA Communications Technology

(India) Private Limited, Bangalore from June-2018

Worked as Layout Engineer (Client: ARM Inc.) for Exiger Technologies India Private Limited, Bangalore.

B.Tech (ECE) from Kakinada institute of Engineering and Technology (affiliated to JNTU Kakinada), with 75.20%.

Diploma (ECE) from A.A.N.M. & V.V.R.S.R. Polytechnic (affiliated to SBTET Hyderabad), with 82.3%.

SSC from Ravindra Bharathi public school, Vijayawada, with 80.2%. ANALOG LAYOUT SUMMARY

PROFESSIONAL EXPERIENCE

ACADEMIC CREDENTIALS

Layout : Cadence Virtuoso Layout Editor (L, XL)

Verification Tools : Calibre, PVS, ICV, Pegasus for LVS, DRC, DFM, Antenna checks and density fix

Operating Systems : Unix/Linux, Windows XP/7/10

TSMC-5nm TX:

CMOSCLOCKS:

• Worked on floor plan, block placement, power and clock signal routing.

• Worked on internal blocks like DIV2(28G) and DIV4(14G), PI.

• Customized MOM caps to Meet the Area Requirement in PI block.

• Complete verification of all blocks LVS, DRC & Manual dummy fill. CLK2_DIST:

• Worked on floor plan, sub block placement, power and Clock Signal and Routing.

• Worked on internal blocks like pre amplifier, Clock inverters, resistor arrays .

• Clock input/output routing has been done in clock tree structure within the half cell to match the nets from Channel Spine.

• For pre_amplifier used common centroid matching technique for differential/input pairs, the devices are split into unit cells to achieve better matching within the half cells.

• Worked on manual density fill for the entire block and fixed EM violations.

• Complete verification of all blocks LVS, DRC, Latch up, Antenna fixes. MUX_TOP:

• Implemented MUX_SEG (64x8) as unit which is Replicated 13 Unit in MUX_TOP.

• Floor plan for MUX_TOP between Driver and Digital Environment.

• Customized MIM cap(Decap) w.r.t power routing.

• Complete verification of all blocks LVS, DRC, Latch up, Antenna fixes. TX/RX Spine Block:

• Worked on top level floor plan, block placement, power and signal and routing

• Worked on High speed internal blocks like ILO(28G), Input Driver, Phase Rotator(28G) etc.

• Complete verification of all blocks LVS, DRC, Latch up, Antenna & MIM violation fixes. Physical Cell Library:

• Developed the Physical cell templates to meet the layout environment (Boundary Cell) for different Channel length which we used instead of Fluid guard ring.

• Implemented Standard MOS templates for various channel instead on P-cell usage. SKILL SET

PROJECTS HANDLED

TSMC-7nm:

Voltage Regulators:

• Device placement, floor planning, input & output signal planning,

• Worked on three different types of regulators (0.9V, 1.2V & 1.5V) layouts which needs to carry high current and met the EM challenges.

• Worked on the bleed circuit for corresponding to the regulators

• Complete verification of LVS, DRC and density fix. Dual Channel Spine TX/RX:

• Top level placement, floor planning, power and clock signal routing.

• Worked on the internal blocks like ILO, RESBUF, resistor arrays.

• Worked on T-Line for Clock signals from PLL to TX and RX.

• Used inter digitization matching pattern for current mirrors and half cell structure for amplifiers to match input/output signal with minimal parasitic mismatches.

• Complete verification of all blocks LVS, DRC, Latch up, Antenna violation fixes. Physical Verification:

• Serdes Level LVS,DRC, density fill verification for 8-Lane. Digital cells:

• Worked on basic digital cells, multiplexers, flip-flops and latches.

• Worked on customized p-substrate unit, which provides isolation between analog and digital circuitry.

• Complete verification of all blocks LVS, DRC & density fixes.

• Presently working on 7LPP and know Architecture evaluation level layout design.

• Supported layout for initial analysis for the beta ratio and stage ratio analysis, Layout

• Architecture (multitrack Analysis, DRC feasibility feedback to Foundry) .

• Developed Base library in multiple tracks.

• Developed multibit & sync flops (2bit and 4bit).

• Mostly worked on flops designing and optimization. Almost done all combinational and sequential and complex logic cells

• Knowledge on PPA (flops) and EM cleaning for layout.

• Developed libraries like LPK & ECO in 6track, 7.5Track and 9track.

• Library QA checks and Post Layout Simulations.

Father’s Name : Venkateshwara Rao Manchineella

Sex : Male

Nationality : Indian

Date of Birth : 25-Aug-1993

STANDARD CELL LAYOUT SUMMARY

PERSONAL PROFILE

Contact this candidate