SANKET LAXMAN ZADE

**** ******* *****, ******* **,21227 adgqd4@r.postjobfree.com 667-***-****

EDUCATION

University of Maryland Baltimore County, Baltimore, Maryland Dec 2020(expected) Master of Science in Electrical and Electronics Engineering 3.26/4 St. Vincent Pallotti College Of Engineering and Technology, India June 2013 - May 2017 Bachelor of Engineering in Electronics & Telecommunication Engineering First Class TECHNICAL SKILLS

Programming languages: C, C++, Java, C#, Embedded C, VHDL, Verilog, System Verilog, PLC, Python Database: MySQL

Software Packages: MS Office, Android Studio, NetBeans, MATLAB, Multisim, Unity 3d, Xilinx ISE, Pspice, Asterisk PBX, AutoCAD, RS Logix, Quartus Prime, ModelSim Altera, Altium, OrCAD, Proteus, ADS, FEM, LTspice Hardware Platforms: Arduino, Raspberry Pi, ATmega328, Altera FPGA, ARM, NIOS Operating Systems: Windows, Linux

Electronic Components: Oscilloscope, Spectrum Analyzer, Multimeter, Diode, Transistor, Filters, Amplifiers, Motors RELEVANT COURSES

Electronics Devices & Circuits, Signal & System, Digital Signal Processing, Control Systems, Network Analysis, Microcontroller & Microprocessor, Analog Circuit Design, Digital Circuits & Fundamental of Microprocessor, Semiconductor, Advanced Computer Architecture, Wireless Sensor Networks, Reconfigurable System Design EXPERIENCE

V S Informatics, Nagpur, India: Electrical Engineer (May 2017 - May 2018)

• Worked on Digital Circuit Design (RTL Design, Gate Level Simulation, Synthesis, Timing Analysis)

• Performed Embedded System project using ARM processor and Atmega328 microcontroller

• Designed Analog Circuit using Multisim, Pspice, OrCAD (PCB Design), Proteus, LabView PROJECTS

64-bit Booth's Multiplier Algorithm November 2019 - December 2019

• Demonstrated 64-bit Booth Multiplier using case statement based state machine on Cyclone V FPGA

• An efficient custom module that directly attaches to the Avalon Bus to accelerate the software implementation

• (Use: Verilog, Quartus Prime, ModelSim Altera, IP Core, Custom Component, RTL Design, Synthesis, Testbench, Netlist, Place and Route)

Car Parking System in VHDL using Finite State Machine (FSM) August 2016 - November 2016

• Parking system implemented using Finite State Machine has two modules Identification and Slot Checking modules.

• Modules tested and verified on FPGA using RTL and Testbench

• (Use: Stepper Motor, Sensor interfacing, LCD, VHDL, Xilinx ISE, RTL Design, Synthesis, Testbench, Netlist) Designed Second-order Butterworth Filter for Audio System November 2017 – January 2018

• Designed Second-order Butterworth Filter for high quality audio system

• Filters out unwanted signal to provide high quality output

• (Use: Amplifier, Resistors, Capacitors, Power Supply, Multisim, Breadboard, Soldiering, OrCAD, Oscilloscope) Water Level Alarm Circuit October 2016 – December 2016

• Produce an alarm when water rises above level using Astable Multivibrator made from a 555 timer IC on PCB

• Implemented using Microcontroller for automatic ON/OFF

• (Use: IC 555, Multivibrator, Multisim, Breadboard buzzer, Pspice, Altium,) ACTIVITIES

● International Robotics Challenge, 2015 : Top 10 in India’s Biggest Robotic Event

● Best Innovation Awards 2017: Reached final round .

● Paper Publications : “Virtual Calling Services”,“ Multi Display System Using CC2500”, “Intelligent Humanoid Legs” published in International Journal Of Advance Research And Innovative Ideas In Education. CERTIFICATES

● Internet of Things -University of California, San Diego

● FPGA Embedded Design, Part 1 & 2 – Verilog and Basic Training of FPGA

● Interfacing with Raspberry Pi - University of California, Irvine

● Embedded Software and Hardware Architecture

Contact this candidate