Alaa Abdullah (Al-taee), Ph.D., P.Eng.
Looking for the Silicon Design Engineer 2 position (Requisition Number: 80621) available in your AMD company located in Markham, Ontario, Canada.
SUMMARY OF QUALIFICATIONS
• Academic research & teaching experience for more than twelve years.
• Industrial engineering experience for more than nine years.
• Industrial engineering research experience for one year.
• Published fifteen journals and conference papers.
• Two layout chips had been fabricated in Canadian Microelectronics corporation using 65 nm technology.
• Deep expertise in analog IC design flow and some exposure to digital IC design flow.
• Strong background in transistor-level for high-speed circuit design including both CMOS and Bipolar transistors.
• Experience in designing of low power CMOS voltage-controlled oscillators, phase-locked loops and adaptive decision feedback equalizer (Adaptive DFE).
• Skills in using Cadence (Specter analysis, Virtuoso, LVS, DRC, XL layout design), VHDL, H-Spice, P-Spice, Maple, Multisim and Simulink, Quartus II, and Latex.
• Management skills in coordinating project’s teamwork and work under pressure.
Ph.D. in Electrical and Computer Engineering from Ryerson University, Toronto 2014.
Dissertation: “Adaptive Decision Feedback Equalization for Multi-Gbps Serial Links”.
M.A.Sc. in Electrical and Computer Engineering from Ryerson University, Toronto 2010.
Thesis: “On-Chip Interconnects Modeling and Timing Driven Buffer Insertion”.
B.A.Sc. in Electrical and Communications Engineering from University of Technology, Baghdad in 1998
Project: Computer Aided Design.
RLT-Assistant Professor, Georgia Southern University, Georgia, USA 2018-2020
Assistant Professor, Australian University of Kuwait, Kuwait 2015-2018
Postdoctoral Research Associate, Ryerson University, Toronto 2014-2015
• Electric Circuit I: Ohm’s Law, KCL, KVL, Nodal and Mesh Analysis, D.C Circuit Analysis, A.C Circuit Analysis, Half-Wave Rectifier, Full-Wave Rectifier, RL Transient Response, RC Transient Response, and RLC Transient Response.
• Electric Circuit II: Diode, PNP and NPN BPL Transistor, PMOS and NMOS Transistors, Sizing and pull-up and pull-down Circuits, Op-Amplifier as Summer, integrator, Differentiator, etc.
• Digital Design Circuits: Computer Systems and Digital design principles, architectural concepts, Boolean algebra, number systems, combinational data path elements, sequential logic and storage elements. Design of DRAM control and I/O bus.
• Digital Design Lab: Logic Circuit Design in DE2 and Bread Board, Logic Circuit Design Using VHDL Code, Quartus and DE2 Board, and State Machines Design in VHDL and Quartus.
• Low Power Digital Integrated Circuits Design: Static CMOS, Dynamic CMOS, Transmission Gate, basic logic gates, combinational and sequential circuits, arithmetic building blocks such as adders and decoders, MOS transistor with I-V equations and the different areas of operations, static (DC) and dynamic (transient) behaviors for an important building block and CMOS inverter
• VLSI Circuits Design: fundamentals of MOSFETs, noise of MOS devices, single-stage amplifiers, differential amplifiers, voltage comparators, phase-locked loops, delta-sigma analog-to-digital converters (fundamentals of analog-to-digital converters, sampling of band-limited signals, noise bandwidth of amplifiers, under-sampling of broadband noise, switched capacitor networks, switching noise, analog and digital grounding.
• 1mm/1mm chip layout based on 65nm technology had been fabricated in Canadian Microelectronics Corporation CMC for Adaptive Decision Feedback Equalizer ADFE utilizing Minimum jitter for Gbps serial links.
• 1mm/1mm chip layout based on 65nm technology had been fabricated in Canadian Microelectronics Corporation CMC for Adaptive Decision Feedback Equalizer ADFE employing Hexagon EOM for Gbps serial links for Gbps serial links.
• Designed a Power-Efficient CDMA-Based Transmitter for High-Speed Serial Links in Cadence- 65 nm Technology. This project was financially supported by Natural Science and Engineering Research Council of Canada and Computer-Aided Design Tools from CMC Microsystems.
• Designed an RC Model for On-Chip Interconnects in H-Spice.
• Designed a Phase Locked Loop (PLL) in Cadence- 65 nm Technology
• Designed a Full Adder using VHDL Coding and Digital Design Flow.
• Designed a CMOS adaptive engine has a decoder with three charge pumps to provide variable steps control signals for DFE.
• Error detection unit has three CMOS comparators and XOR logic circuit were developed to provide steepest ascent/descent fix control signals.
• 10-PRBS with CMOS differential pair driver, 3-tap DFE architecture with continuous-time liner equalizer CTLE, three separate CMOS charge pumps with fix steps, and three comparators with three sampling points were designed as an Adaptive Decision Feedback Equalizer. The design was simulated and validated using Specter from Cadence in an IBM 65 nm 0.8V CMOS technology.
• CMOS Phase Locked Loop including phase detector, low pass filter and five CMOS quadrature voltage controller oscillator (VCO) cells (ring oscillator) with control circuit were designed and locked. The design was simulated and validated using Specter from Cadence in an IBM 65 nm 0.8V CMOS technology.
• A schematic and layout with routing and power distribution for full adder were designed utilizing VHDL coding in Verilog. The design was simulated and validated in FPGA.
COLLABORATIVE RESEARCH IN INDUSTRY
Researcher, Semtech/Snowbush Co., Toronto 2011-2012
Presented design techniques for decision feedback equalization of multi-Gbps serial data links: a state-of-the-art review.
Invented of a new hexagon EOM technique to improve the performance of serial links.
Engineering Supervisor, AXA Electric Co.-Toronto 2002-2007
Provided time management for the project
Involved in the estimation of cost factor for the project
Supervised electricians at the job sites
Engineering Manager, EIC Co. -Baghdad-Iraq 1998-2002
Supervisor for TV line product
Supervisor for electronic design group (printed circuit boards)
Manager of electronics maintenance team
 Alaa Al-Taee and F. Yuan, "An Edge-Based Dual Adaptive Decision Feedback Equalizer for Gbps Serial
Links," Analog integrated Circuits and Signal Processing (Springer), Vol.90, No.2, pp.399-409, Feb.
 Alaa R. Al-Taee and F. Yuan, “Adaptive Decision Feedback Equalizer with Hexagon EOM and Jitter
Detection”, Circuits, Systems, and Signal processing, Vol. 35, No.7, PP. 2487-2501, Jul. 2016.
 A. Al-Taee, F. Yuan and A. Ye, "Adaptive decision feedback equalizer with hexagon EOM and bang-bang
jitter detection," Circuits, Devices, and Signal Processing (Springer). Vol.22(3), pp. 373-388, Sept. 2015.
 Alaa R. Al-Taee, F. Yuan and A. Ye, "Minimum jitter adaptive decision feedback equalizer for Gbps serial
links," IET Journal of Engineering, Vol.2, No.1, pp. 1-7, Jan. 2015.
 Alaa R. AL-Taee, F. Yuan, and A. Ye, “An improved RC model for VLSI interconnects with its applications
to buffer insertion,” Analog Integrated Circuits and Signal Processing (Springer), Vol.79, No.1, pp. 105-
113, April 2014.
 F. Yuan, A. Al-Taee, A. Ye, and S. Sadr, "Design techniques for decision feedback equalization of multi-
Gbps serial data links: a state-of-the-art review," IET Circuits, Devices, & Systems. Vol.8, No.2, pp.118-
 A. Al-Taee, F. Yuan, A. Ye, and S. Sadr, "New 2D eye-opening monitor for Gbps serial links," IEEE
Transactions on Very Large Scale Integration Systems, Vol.22, No.6, pp. 1209-1218, June 2014.
 Alaa R. AL-Taee, F. Yuan, and A. Ye, “A Power-Efficient 2-Dimensional On-Chip Eye-Opening Monitor
for Gbps Serial Links,” Analog Integrated Circuits and Signal Processing (Springer), Vol. 76, No. 1, pp.
117-128, July 2013.
 Alaa R. AL-Taee, F. Yuan, and A. Ye, “A new power-efficient CDMA-based transmitter for high-speed
serial links,” Analog Integrated Circuits and Signal Processing, Vol.71, No.2, pp.1-7, Feb. 2012.
 A. Al-Taee, F. Yuan, and A. Ye, "Minimum jitter adaptive decision feedback equalizer for 4 PAM serial
links," Proc. IEEE Int'l Symp. on Circuits and Systems, 2015.
 Alaa R. AL-Taee, F. Yuan, A. Ye, “A New Adaptive Decision Feedback Equalizer Using Hexagon Eye-
Opening Monitor for Multi-Gbps Data Links," IEEE Int'l Symp. on Circuits and Systems (ISCAS),
Melbourne VIC, Australia, pp. 2137-2140, June 2014.
 A. Al-Taee, F. Yuan, and A. Ye "Two-dimensional eye-opening monitor for serial links," Proc. IEEE Mid-
West Symp. Circuits and Systems, pp. 181-184, Columbus, 2013.
 A. Al-Taee, F. Yuan, and A. Ye "A new CDMA transmitter for high-speed serial links," Proc. SIECPC-
2013, pp.1-4, 2013.
 A. Al-Taee, F. Yuan, and A. Ye "A new simple RC modeling for on-chip interconnects with its applications
to buffer insertion," Proc. SIECPC-2013, pp.1-4, 2013.
 Alaa R. Abdullah, Adnan Kabbani and Kaamran Raahemifar,“ Mapping The AWE-RLC Model Into a
Simple RC Circuit With its Application to Buffer Insertion” IEEE Canadian Conference on Electrical and
Computer Engineering (CCECE11), pp. 152-155, Niagara Falls, April, 2011.
CITIZENSHIP AND LANGUAGE SKILLS
Canadian, fluent in English and Arabic
Available upon request