M SAIKUMAR

Email:adg997@r.postjobfree.com

Cell: +91-799*******

Executive Summary:

• demonstrated working experience in semi conductor industry as a Physical design engineer at Beta-Scientifics, Bangalore.

• Proficiency in Analyzing & Debugging timing reports and fixing timing and DRV's.

• Good Timing Analytical Capability using Prime Time (Synopsys).

• Experience in Place and Route using ICC & ICC2 (Synopsys).

• Hands on working experience on lower technology nodes 16nm, 22nm, 130nm technology nodes.

• Good knowledge of Floor planning, Power planning, Placement, CTS, Routing, Static Timing Analysis (STA), DRC cleanup and LVS cleanup as well.

• Working Experience on analysis of timing paths, timing reports, fixing ofsetup/hold.

• Skew Optimization, DRC with Calibre.

• Generated and analyzed standard cell custom layouts by using Mentor graphics pyxis tool.

• Interested to work with ASIC/SOC level Backe-end domain (Analog&mixed signal design and physical design).

• Good understanding and implementation of PSPICE code for the basic circuitslike two-stage op-amp etc., in analog domain.

• Good at debugging and problem solving.

• Worked on Block-level Design Implementation.

• Hands on working experience of DRC and ECO fixing.

• Hands on working experience on UNIX/LINUX environment.

• Knowledge on tools related to Physical design:

• PnR: Synopsys ICC, Synopsys ICC2

• Timing closure: Prime time

• DRC: Calibre

• Std. cell Layout design: Mentor graphics Pyxis

Work Experience:

Company Duration

Beta Scientifics May 2018 - Present

Technical Skills:

Programming/Scripting

Languages

C, Verilog, TCL/Tk.

Area of Interested to work Physical design, analog design Tools Synopsys ICC2(PnR), Synopsys ICC, Mentor graphics Pyxis(std. cell design), Xilinx 14.7, ORCAD PSPICE analog simulator, Digital schematic(std. cell design), Prime time(STA), Calibre(PV).

Projects:

Industrial project summary:

PROJECT 1: PNR Implementation of Block-level ASIC design(GroupCh_Block) Description:

• 16nm technology

• 56 macros

• Instant count 1.2M

• 11 layers

Tasks Handled:

• IO planing and IO port assignments.

• Avoid congestion issue by proper blockages and regions & Meeting target congestion.

• Improving timing in placement.

• Implemented buffer & Inverter insertion as per logic requirement.

• STA Analysis and generation of timing closer fixes.

• Done multiple experiments to reduce congestion and timing.

• Done Placement experiments for reducing the congestion of the particular modules in which more number of AOI cells are present.

• Tried different techniques in ECO phase to reduce DRC’s and shorts in routing critical regions.

PROJECT 2: HP101 – ARM graphics processor

Role: Responsible for Complete PnR, Timing Closure, Physical Verification Description:

• Instances - 0.2 Million Instances, Frequency - 500Mhz

• Tech node:- 55nm

Tool Used : ICC2

Challenges:

• Placing ports base on connectivity.

• Placing macros to avoid channel creation due to large size.

• Closing timing due to high logic depth of some paths. PROJECT 3: A Robust CTS algorithm using the H-Tree to minimize local skews of higher frequency targets of the designs.

Description:

• 22nm technology

• 65 macros

• Instance count 46k

• 9 layers

Deliverable/Challenges Faced:

• Block Level Floor planning and placement.

• Meeting target congestion.

• CTS using H tree Methodology.

• Routing & Timing closure (Setup & Hold)

• DRC/LVS Clean up

• Fixing Antenna violation

Academic project summary:

PROJECT 1: Development of PSPICE simulation of two-stage Op-amp Description:

• Developed PSPICE code for two-stage op-amp contains around below 200 transistors. PROJECT 2: Complex multiplier using VerilogHDL

Description:

• Designed RTL code for 2-bit complex multiplier using VerilogHDL. PROJECT 3: Traffic density management system

Description:

• Observation of no.of vehicles per unit area by using IR sensors and other sensing elements(Sensors).

• Arduino board usage and Interfacing Arduino board with LCD. Educational Qualification:

• MTech in VLSI Design from SVEC, Tirupati, 2020 with 84.95% aggregate.

• BTech in Electronics and Communications from SVCE, Tirupathi, 2017 with 6.1 aggregate.

• Intermediate(XI, XII) in MPC from NRI Jr. college, Tirupati, 2013 with 65% aggregate.

• SSC in State Board from M.C.H. School, Somala, 2012 with 65% aggregate. Personal Details:

M Saikumar S/o Mr. M Babu

Tirupathi

Chittoor (Dist.,)

A.P, India

517501.

M SAIKUMAR

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