SHREYANSH VYAS
Software Developer & Engineer
Phone: 610-***-****
Email: adg21q@r.postjobfree.com
Objective: Candidate with a Master’s in Software Eng. looking for a challenging position to create value for an organization. CORE COMPETENCIES
• Microsoft Office Suite • SharePoint • Cloud technologies (AWS & Azure)
• Agile/Scrum • Visual Studio, Vivado,
Docker, Tableau, Git
• C, Java, Python, MATLAB, SQL,
C++, React, Verilog
WORK EXPERIENCE
M&P Technologies, LLC – West Chester, PA (Summer 2020) Junior Developer - Intern
Position Overview: Engaged to work closely with a vendor team on development effort to deliver interactive website using various plug-ins. Key responsibilities included:
• Created automation that integrated with GitLab for code branch pull and package deployment.
• Worked closely with Solution Designers to create process flow technical artifacts that aligned with Product Owner.
• Created and estimated user story points working in JIRA.
• Conducted Unit, Integration and E2E testing before deploying the code to a higher environment. Penn State University (2018 – 2019)
Research Assistant
Position Overview: Engaged to conduct extensive research on transducers to generate passive cavitation images using ultrasound treatment. Key responsibilities included:
• Capture passive cavitation images using MATLAB tool to regiment drug delivery to the patient’s artery walls without performing invasive surgery.
• Utilized software to simulate various frequencies and signals to obtain different passive cavitation images that assisted in finding the location of the aberration.
ACADEMIC EXPERIENCE
• Created a defined software process by integrating scrum and agile methodologies within development lifecycle.
• Constructed a database in Oracle that created and translated an ER model into a normalized relation schema and using SQL implemented and manipulated the data to meet the requirements of the organization.
• Developed a block chain functionality to keep track of user transactions and block validity in a peer to peer system using Kotlin and React.
• Applied a device driver using C programming language to open, read, write, and close multiple files from memory.
• Designed and implemented a five-stage pipelined CPU on FPGA in Verilog using the Vivado Xilinx design package.
• Implemented a python code to create a proxy server that was able to cache web pages, and python code that was able to send/receive data through a UDP socket.
EDUCATION
Master’s in Software Engineering (Est. Spring 2021) Drexel University Bachelor of Science in Computer Engineering Penn State University