Design Processor

RESUME

Syed Ameerunnisa Begum

**-**-**/*/*,

Phase 5, room no.2,

Vuda nagar,

Kurmannapalem,Pin : 530049 *********@*****.***

Visakhapatnam, AP. +91-630*******

OBJECTIVE:

Looking for an opportunity in a prestigious organization where I can improve my technical and analytical skills that can be used for the development of an organization as well as my career, and be a part of a progressive growth oriented organization that gives me scope to enhance my knowledge and skills to cope up with the latest trends. EDUCATIONAL QUALIFICATION:

1 M.Tech (Instrumentation & Cntrl Systm) (Oct 2013-Oct 2015), JNTUK. 78 % 2 B.Tech (Electronics & Instumentation) (2008-2012), LBRCE (JNTUK), 79.64%. 3 Intermediate (2006-2008), Bharateeya Junior College, Gudavalli, 90.10%. 4 SSC (2005-2006), Z.P.High School, Board of Secondary Education, Sathyalapadu, 92.67%. TECHNICAL SKILLS:

ProgrammingSkills : C Language, Python, Data Science Subjects : Electronics, Instrumentation, Control Systems Experience: worked as Operations representative from Jan 2019 to Mar 2019 PROJECT PROFILE:

PROJECT: Implementation of a 32 bit RISC processor with memory controller by usingVHDL

DESCRIPTION: The design of a RISC processor with memory controller is done inthis paper. For the best use of memory, this processor contains a memory module and control unit which is included in the processor design. This Processor embodies 15 basic instructions involving Arithmetic, Logical, and Data Transfer andcontrol instructions.To RESUME

implement these instructions the design incorporates various design blocks like Control Unit

(CU), Arithmetic and Logic Unit (ALU), Accumulator, Program Counter (PC), Instruction Register

(IR), Memory and additional logic. A new architecture is implemented for the proposed RISC processor with 32 bit input. The processor has small instruction set and control logic design is very much simplified. It is basically designed in order to achieve faster executions and the processor can execute each instruction within one clock cycle. All individual logic blocks are simulated using ModelSim Simulator and top module is obtained by connecting all the blocks in an order.

Publication details: Published paper in International Journal of Innovative Researchin Electrical, Electronics, Instrumentation and Control Engineering (IJIREEICE). ACHIEVEMENTS:

Obtained 1443 rank in GATE(Instrumentation)

Stood class second in B.Tech

Stood class second in M.Tech in 1styear

Secured class first in Xclass

Secured first prize in paperpresentation

PERSONAL TRAITS:

Planning and dedicated

Flexible

Sportive

Innovative

PERSONAL DETAILS:

DateofBirth : 06-June-1991

Husband’ sName : P. Aleemulla Khan

Gender : Female

Maritalstatus : Married

Nationality : Indian

Languages : Urdu, English, Telugu and Hindi

DECLARATION:

I do here by declare that the details furnished above are true to the best of my knowledge and belief.

Place: Visakhapatnam

Sig:

(Sd. AmeerunnisaBegum)

RESUME

Date:

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