MUDDUSETTY SIVAPRASAD
E-mail: **************@*****.***
Present Address:
S/O M.Ravindra,
Ground floor, Sai brindhavan apartment,
5th main road, 4th cross, AECS Layout, D-block
Kundhala halli gate, Bangalore,
PIN: 560037,
India
Phone No.:+91-879*******
OBJECTIVE:
To build a career in an esteemed organization where I can utilize my knowledge and skills towards continuous growth, enhance profitability and productivity of the organization. EDUCATIONAL PROFILE:
Course/Degree Board/University Name of the
institution
Year of passing Percentage
Graduation
( B.TECH-ECE)
Jawaharlal Nehru
Technological
University
Ananthapuram,
India
Sir
Vishveswaraiah
Institute of
Science and
Technology,
Madanapalle
2019 76
INERMEDIATE/+2
MPC
Board of
Intermediate
Education,
Andhra Pradesh
Viswam Junior
College,
Madanapalle
2015 89.6
SSC Board of
Secondary
Education
Z.P. High School
Kona
2013 92
ACADEMIC ACHIEVEMENTS:
Secured 3rd in my Matriculation out of 35 students.
Ranked 2nd in the department in terms of CGPA:7.8(up to 3rd Year 2nd Semester).
I was grabbed 1st prize winner contestant in Technical Quiz competition conducted by “Time pass popcorn” in SVTM campus on 8th March 2017.
TECHNICAL SKILLS:
Programming Languages: C, Core java
Operating Systems : Windows, Linux
Packages: MS Office
Software skills: MATLAB, Xilinx ISE
STRENGTHS:
Active, Punctual, Hardworking, Commitment towards work.
Easy adaption to new work environment and Working Independently as well as with team.
EXTRA CURRICULAR ACTIVITIES:
Active participation in quizzes.
Member in National Service Scheme (NSS).
Team leader in academic project
WORKSHOPS ATTENEDED:
Participated in three day national level workshop on “VLSI-VIVADO and BIOPAC for Bio-signal Processing using Wireless Data Acquisition Systems” in college of Aditya College of engineering,Valasapalle,Madanapalle-517325
Participated in three day national level workshop on “Embedded systems (IOT) fundamental applications” in college of SVIST,Angallu,Madanapalle-517325 PROJECT WORK:
Project title: Design of arithmetic & logic unit (ALU) by using novel reversible gates
Duration: From December 20 to March 17
Role: Team leader
Team size: 5
Abstract: In the current scenario, power consumption, speed, size and heat dissipation are the huge challenge in the semiconductor industries. When the size of the single computing element is reduced then the speed can be improved and also if the power dissipation is reduced then the heat dissipation will be less. The Reversible Logic is considered to be the promising technology to the future Quantum computer technologies. The Reversible Logic gates prune the power dissipation to a larger extent. In this Novel Reversible Gates are proposed with Reversibility and Universality. The Arithmetic and Logic Unit (ALU) is designed with the proposed Reversible Gates in Reversible Logic. PERSONAL DETAILS:
Father’s Name : M.Raveendra
Date of Birth : 9th June 1998
Gender : Male
Nationality : Indian
Languages Known : English, Telugu
Permanent Address : s/o M.Raveendra
D.No:1/225, Gudibanda, KotaGudibanda (post), Kalakada (Mandal), Chittoor (Dist.), Andhra Pradesh-517236
Hobbies : Playing chess and Listening to music
DECLARATION:
I hereby declare that the information given above is true to the best of my knowledge and belief. I would keep up to your expectations. I would always be keen to work for the organization. Date:
Place: Bangalore signature