RESUME

SUSHMA KOYELADA,

D/o: K.Srinivasarao,

Door No.: 31-1-101,

Kummaraveedi,Allipuram, Email: adfoet@r.postjobfree.com

Visakhapatnam-530004. Mobile: 738-***-****

Career Objective:

To utilize my technical and professional skills in the best possible way to achieve an organization’s goals and help lead the organization to reach the zenith. To secure a challenging position that gives ample scope to fulfill professional and personal goals and to work for development of an organization to the highest possible limit.

Academic Qualifications:

Qualification

Specialization

College

University/Board

Year Of Passing

CPGA / %

M.Tech

ECE

(VLES)

Vignan’s Institute Of Engineering For Women, Visakhapatnam

JNTU-K

2017

75.28%

B.Tech

ECE

Sanketika Institute Of Technology And Management, Visakhapatnam

JNTU-K

2014

68.39%

Intermediate

M.P.C

NarayanaMahilaJunior College, Visakhapatnam

State board

2010

81.1%

10th class

-

Priyanaka’sVidyodaya High School, Visakhapatnam

State board

2008

65%

Employement History:

Assistant Professor/Junior Research fellow (JRF) April 2017-Present @Vignan’s Institute of Engineering for Women, Visakhapatnam. As JRF worked with Mentor Graphics for ASIC design flow (Semi-custom and full custom), IP core integration catalog using Vivado design suite, System generator using Vivado and Matlab Simulink blocks.

Computer Skills:

Operating Systems: Windows XP/98,Windows 7 Office

Designing Software: XILINX, Tanner EDA, MentorGraphics, Vivado

Languages: C,VHDL

Project:

Have done a major project on “GSM BASED HOME AUTOMATION AND SECURITY SYSTEM” in Under graduation.

Have done a major project on “INVESTIGATION ON THE PERFORMANCE OF FLOATING POINT MULTIPLIER USING DELAY INSENSITIVE DESIGN APPROACHES” in post graduation.

Publications :

The paper on “An alternative delay insensitive paradigm for low power synchronous digital circuit” was published in IJEEE,Vol No.8, Issue 02, JULY 2016,ISSN 2321 2055(O).

The paper on “Energy Aware IP Shifter for DSP Processors using MTD3L Asynchronous Approach” was published in IOSR Journal of VLSI and Signal Processing (IOSR-JVSP), Vol No.6, Issue 6, Nov-Dec 2016, ISSN 2319-4200.

The paper on “Design of Energy Efficient Dual Spacer Delay Insensitive Ripple Carry Adder with better Slew Rate” was published in IJET, Vol No.8, Issue No.6, Dec 2016-Jan 2017, ISSN 0975-4024.

The paper on “Energy Efficient IEEE 754 floating point multiplier using dual spacer delay insensitive logic” was published in Circuit World-Emerald, Vol No.43, Issue No.2, May 2017, ISSN 0305-6120.

The paper on “Evaluation of Dual Rail Complete Detection Circuitry using Asynchronous Delay Insensitive Frameworks” was published in IJSSST, 2018, ISSN 1473-8031.

Personality Traits:

Strong Interpersonalskills.

Ability to work in the time bound crisis situation.

Can work efficiently in a team as well as individually.

Sincere & Hardworking.

Personal Details:

Name : K.SUSHMA

Father’s Name : K. SRINIVASA RAO

Date of Birth : 22nd February, 1993

Marital Status : Unmarried

Religion : Hindu

Nationality : Indian

Gender : Female

Languages Known : English, Telugu

DECLARATION

I hereby declare that all statements made in the application are true, complete and correct to the best of my knowledge and belief.

Place: Visakhapatnam K.SUSHMA

Date: 29th August, 2020.

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