Design Engineer

MANJUSHREE SHIVARUDRAIAH

Email: **********.*************@*****.*** Phone: 657-***-****

PROJECTS

ASIC design of Hardware accelerator for Histogram Equalization

-Implemented in Verilog as a pipelined processor to maximize throughput.

-Simulated using ModelSim and synthesized using Synopsys Design Vision. Verification of a Switch RTL core using System Verilog’

-Built a complete Verification environment for functional coverage of a Network Switch using System Verilog.

DFT implementation on multiple design units of varying complexity

-Worked on multiple target design units with flopcount ranging from 650 to 22000 flops.

-Performed MBIST Insertion using Tessent Shell

-Performed EDT/compression to reduce test time and test data volume using Tessent TestKompress

-Performed Synthesis using Synopysys Design Compiler

-Performed scan-insertion on netlists. Used Tessent Scan to perform DRC analysis to check feasibility. Improving the Test coverage and considered lesser number of patterns for testing the design.

-Generated ATPG patterns for the target design using Tessent FastScan Generated Patterns for stuck at and atspeed models. Observed coverage numbers and optimized the design by fixing violations extracted from fault reports.

-Performed no-timing simulation using Questasim.

Automatic test pattern generation using BIST architecture

-Simulated various LFSR’s to determine the best among them to generate test patterns. Design and verification of Interrupt Controller

-Designed in Verilog to collect Interrupts from various peripheral controllers and forwards the interrupt to processor on priority basis. It works until all the interrupts are serviced by processor.

-Interfaces with processor on one side using APB interface and other side with peripheral controller from which it gets interrupts.Responsible for functional verification of the same using System Verilog. Efficient Interleaver Design for MIMO-OFDM based Communication system using FPGA

-Memory proficient and faster Interleaver is designed and comparing results with a reference paper “Design and implementation of area efficient Interleaver for MIMO-OFDM systems”.

-Providing future upgrades to the IVector and documenting all the necessary contents for future use. TECHNICAL SKILLS

Programming Skills: C, C++

Hardware Languages: Verilog, Systemverilog

Scripting Languages: Python, Perl, tcl

Tools:Tessent Scan, TestKompress, Tessent Fastscan, QuestaSim, ModelSim,LTspice, MATLAB,Multisim Operating Systems-Windows, Linux

CERTIFICATIONS

Design for Testability(DFT) certification in VLSIGURU Training Centre, Bangalore. Gained experience on all aspects of testability flow including testability basics, SoC scan architecture, different scan types, ATPG DRC debug, ATPG simulation and DFT diagnosis. Also worked on JTAG, Memory BIST, Logic BIST, test compression techniques and hierarchical scan design. ACADEMICS

Master’s in Computer Engineering (GPA- 3.7/4.0) (Graduation: May 2020) California State University, Fullerton Major: Computer Engineering Coursework:

VLSI Testing and DFT Intro to VLSI Design and Computer Organization Mixed Signal IC Design Low Power IC Design Advanced Computer Architecture Digital ASIC Design(Online)

Bachelor’s in Telecommunication Engineering (2012-2016) Bangalore Institute of Technology (Visvesvaraya Technological University) PROFESSIONAL EXPERIENCE

Senior Analyst Engineer in Capgemini Pvt Ltd, India. (September 2016-January 2018)

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