Design Engineer Designer

Tejas Limbasiya

Hello :- +91-942**-*****

Email :- ******************.**@*****.***

Work Experience

Currently I am working at System Level Solutions India PVT. LTD. as an RTL Design Engineer since 13th April, 2017.

Skills

Languages Verilog, System Verilog, C (basics), TCL commands FPGAs

Intel 5 and 10 series - MAX, Cyclone, Arria, Stratrix Xilinx : Spartan-6

Protocols WTB, AMBA, AXI, I2C, UART, SPI

Tools

Quartus, Modelsim, Vivado, Eclipse, MCUXpresso, LPCXpresso, Code Composer Studio, GUI Composer

Hardware Expertise in Hardware debugging, good knowledge of Analog circuits Version Control

System

SVN, Tuleap, Git, Gerrit

Misc.

High-level synthesis, STA, SDC files, Architecture documentation, Test Reports

Projects

1 WTB Gateway: For Railway application

Duration: 8 months (Dec-2019 to Till date)

Key Roles:

I have been involved in Physical Layer and Link Layer development of WTB i.e. Wire Train Bus Protocol.

Physical Layer: Designed Manchester Encoder and Decoder

Link Layer: Designed Packet Encoder and Decoder with Auxiliary Process FSM and Main Process FSM.

The implementation has been verified with respect to functional simulation using Modelsim and validated with hardware.

2 Vehicle Control Unit: For Railway application

Duration: 10 months (Jun-2019 to Mar – 2020)

Roles:

To access Digital Input and Output signals through IO-Expander using I2C interface.

To prepare LPC to FPGA memory bridge

To read corresponding analog channels from remote unit through UART interface.

To design software using C to access Digital IOs. The implementation has been verified with respect to functional simulation using Modelsim and validated with hardware.

3 Intelligent Gate Interface: For Railway application Duration: 18 months (Jul-2018 to Jun – 2019)

Implementation:

Facilitated design to calculate below parameters.

RMS, mean, average, di/dt, dv/dt, maximum and minimum of Analog voltage, current channels and temperature.

Interface of ADC and DAC using SPI protocol.

Implemented Remote System Update feature using RSU IP core of Altera.

Development for filtering, processing, monitoring and controlling of PWM signals according to application.

4 Auxiliary and Traction Converter: For Railway application Duration: 18 months (Oct-2017 to Mar – 2019)

I was responsible to prepare asynchronous memory interface between 3 DSP controllers and 1 LPC controller. Bridge facilitates asynchronous read/write operations among all controllers.

I have also interfaced ADC and IO-Expander using I2C protocol. 5 I2C IP Core: IP core design

Duration: 6 months (Apr-2017 to Oct - 2017)

Filter designing for the I2C bus IP core.

Prepared GUI for the I2C IP using TCL commands. It helps user to have easy and handy access of IP in Quartus Platform Designer (formerly known as Qsys designer). Education

2011–2015 B.E Electronics & Communication Engineering, GTU - Gujarat. CGPI – 8.37

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