BHANU PRAKASH SHARMA 312-***-**** adf722@r.postjobfree.com Chicago, IL linkedin.com/in/bhanu-prakash-sharma/ Digital Design Processes RTL Design SOC Design Timing Analysis ASIC Design Signal Processing FPGA Design

• Pipelined MIPS Processor Design: Designed a 32-bit, 5-stage pipelined MIPS processor with Datapath and controller in System Verilog using Quartus Prime design software. Verified processor functionality with test bench containing Machine code.

• ASIC Designs: Applied the academic knowledge in successfully designing Safe-Vault, Stopwatch, Cache (Fully and Set associative designs), Shift and Add Multiplier using Finite state machine, Content Addressable memory, Pattern Predictor.

• Expertise: Signal processing, Design Testing, SoC Design, ASIC Design, FPGA Design, Analog Design, IP based design, Microarchitectures, Seamless Module Integration, Stakeholder Relationship Management, Cross-Functional Collaboration, Systematic Problem Solving

EDUCATION

Master of Science in Electrical and Computer Engineering, University of Illinois GPA: 3.8 2020

• Courses: Introduction to VLSI, Advance VLSI, HDL-Based Digital & Computer System Design, Digital System Design, Advance Computer Architecture, Advance Microprocessor Architecture, Neural Networks, Digital Signal Processing-II, Computer Vision. Bachelor of Technology in Electrical Engineering, UPTU University GPA: 3.6 2013

• Courses: Basic System Analysis, Electrical Measurements & Measuring Instruments, Analog & Digital Electronics, Microprocessors, Fundamentals of Electromagnetic Theory, Elements of Power System, Power Electronics, Control Systems.

• Secured 1st place in the Robo Racing contest; built an autonomous path follower; part of a 2-member team.

• Technical Skills: Verilog, System Verilog, Xilinx ISE, Cadence Virtuoso, Quartus, Modelsim-Altera, Arduino, x86 Architecture, MIPS Architecture, DFT, UART,RS485, RS232, I2C, SerDes, SPI, Raspberry pi, Python, MATLAB, R Programming, C Programming ACADEMIC PROJECTS

Single Cycle and Multicycle MIPS Processor Design: Designed and verified functionality of a 32-bit Single Cycle and Multicycle MIPS Processor; Datapath and Controller designs based on FSM; Structural design modelling; Used Quartus prime with System-Verilog. Power Optimization Theory Testing: Implemented and Verified findings of 2 IEEE papers on low power designs; Johnson Counter using clock gating and an adiabatic 4-bit Johnson Counter based on power gating CPAL logic; built circuits for 45nm technology circuits. Achieved a 20% drop in leakage current through clock gating and a 32% drop through power gating. Used NCSU library. MAC Data Paths Designing: Ensured optimal and synchronous circuit performance while developing a MAC data path for a neural network with a 1GHz clock; led 5-member team; calculated component placement. Used basic PMOS, NMOS, and Cadence Virtuoso. Digital filter design: Designed Digital filters (FIR and IIR) in the MATLAB using different algorithms. Used FIR (window based, Frequency sampling based, CLS, Interpolation) and IIR (Butterworth, Chebyshev) to design Low-Pass, High-Pass etc. filters. PROFESSIONAL EXPERIENCE

Volunteer Research Scientist, Electrical and Computer Engineering Department, University of Illinois at Chicago 06/2020 – Present Collaborating with Neurosurgery department to implement the Machine learning models on Low power devices using Neural Network Concepts.

Teaching Assistant, University of Illinois at Chicago 08/2019 – 05/2020 Reinforced learning for 50-100 undergraduate students in the Discrete and Continuous Signal Processing, Intro to Electromagnetics and Application, Circuit Analysis, and Electronics II courses. Led lab sessions to demonstrate basic electrical engineering concepts. Project & Commissioning Engineer, VSM Venture Control Systems, India 10/2015 – 04/2018 Designed and maintained PLC-based and FPGA based motion-control solutions for multiple industries; commissioned 10+ projects. Corrected synchronization, signal, and electrical routing issues between PLC and IO devices; used HMI, SCADA, encoders, sensors, electrical drives. Led identification, troubleshooting, and verification of faulty analog circuits in a 3-member team.

• Commissioned a galvanizing line with a 10-12-member team; conducted cable and IO scheduling for all line operations; ensured correct electrical wiring and routing. Managed client requirements; calculated device placement locations.

• Addressed a safety issue of exploding capacitor banks by advocating to strike a balance between capacitor banks and MOSFET. Previous Experience: Freelance Electrical Engineer (07/2013 – 09/2015); Project Intern, Esmech Equipment (06/2012 – 08/2012).