Electrical Engineer

Akhila Jarabani

+91-799**-***** **************@*****.***

PROFESSIONAL SUMMARY

• Enthusiastic and hardworking Engineer with a master’s in electrical and Computer Engineering and 2 and half years of industry experience

• Proficient in various programming languages like LabVIEW, MATLAB, C, Python and C++.

• Exceptional knowledge of GPU – micro architecture, III-V semiconductor devices and Verification of VLSI systems.

• Extensive knowledge in LabVIEW programming and National Instruments hardware and software.

• Knowledgeable in Semiconductor devices, processing and Computer architecture and design.

• In depth understanding of RTL design, High-level synthesis and Hardware design languages like Verilog

• Strong working knowledge of electronics lab equipment – oscilloscopes, protocol analyzers, Spectrometers, etc.

• General electronics experience designing, troubleshooting, and working with Diodes, Transistors, FETs, CMOS, capacitors and inductors, among others.

• Experience with Simulators like Gem5 along with various ARM based CPU benchmarks.

• An effective communicator in a team with various backgrounds and strong collaborator with excellent analytical and logic skill added on to amazing people skills. Areas of expertise:

• Programming Languages: C, C++, Data Structures, MATLAB, LabVIEW, Verilog, PLC and Python

• Operating Systems: Windows, Linux, Unix and RedHat Linux

• Skills: Microsoft Word, Excel, Power Point, Visio

PROFESSIONAL EXPERIENCE

Test Engineer: 09/18 – Present

Siemens Healthineers Newark, DE

• Analyze the subsystem specifications to arrive at appropriate test conditions.

• Design the test conditions and simulate the scenarios required to perform the key test aspects of the system.

• Arrive at test methods to validate the sub system components available. The sub system components include Stepper/Servo/Dc Motors, Displacement pumps, Vacuum Pumps, Motor Controls, Copley Controllers, Real Time Controllers, Temperature Sensors, Pressure Sensors, Tachometers, Level Sensor, Crash Detection Sensors, Load Cells, Solenoids Valves, Spectrum Analyzers, TED’s and Robotic Arms.

• Test Software Architecture design and development to validate sub system components on Automated Test Equipment (ATE) using National Instruments LabVIEW, LabVIEW OOPS, LabVIEW Real Time, Test Stand, Python, CAN, CAN Open, RS232, USB, IEEE 488, GPIB, I2C and SPI.

• Develop intuitive Graphical User Interfaces (GUI) for testing and unit evaluate the developed software.

• Perform Integration & System Testing on the complete test fixture including the sub system components under test and the test equipment.

• Perform required test analysis and present them to the concerned parties to arrive at key decisions like making any design changes to the subsystem.

• Coordinate with cross functional teams for successful completion of projects. Document test software implementation, test methods and test sequences.

Engineering Intern: 8/17 – 8/18

Artesyn Tempe, AZ

• Responsible for analyzing the architecture and design of various FPGA’s for direct and third-party clients.

• Created Tests and test Environment to meet the design specifications using LabVIEW.

• Worked on various test equipment like Oscilloscopes, function generators, signal generators and numerous power electronic equipment.

• Gained good knowledge in the process of creating the specifications, design and verification of the hardware and software requirements.

EDUCATION

University of Arizona, College of Engineering Tucson, Arizona Master of science - Electrical and Computer Engineering Aug 2015 - May 2017 Jawaharlal Nehru Technological University Hyderabad, India Bachelor of Technology - Electrical and Electronics Engineering Aug 2011 - May 2015

RESEACH PROJECTS

Semiconductor Processing 8/16 – 12/16

• Working on various projects on the approaches to recipes of LPCVD and Etching under different conditions.

• Experience in Micro/Nano fab center at University of Arizona which consists of Class 100 and class 10 clean rooms in studying the properties of Si-wafers under various processes including CMP and Lithography

• Firsthand experience with Equipment used to perform and study an array of fabrication processes, including: ABM mask Aligner, AGS Reactive Ion Etcher, Tempress LPCVD tool, BOC Edwards Auto 306 (E-beam Evaporator), Brewer Science Cee 200 Spin Coater and Solitec Spin Coater. Verilog File Generator 8/16 – 12/16

• Converted a C-like behavioral net-list comprising of operators and operations to be performed along with latency and resource constraints to a Verilog file.

• Created a program in C language to generate the Procedural Verilog file required comprising a High-Level State Machine (HLSM).

• Programmed the sequential statements using Force Directed Scheduling algorithm. Photovoltaics: Solar Energy Systems Lab 1/16 - 5/16

• Studied solar-photovoltaic effects and conducted experiments on the electrical properties and performance characteristics of various PV modules (SunWize SW 60, Amorphous Silicon, CIGS panel) and PV cells. Effects of IQ and ROB on Performance and Energy Consumption 8/15 – 12/15

• Analyzed the effects of various sizes of Instructions queue and Reorder buffer on performance and energy consumption of the system using C++.

• Used Gem5 Simulator on an ARM–based CPU model with benchmarks from the SPEC2006 benchmarks suite

(astar, gromacs, and mcf benchmarks were used).

Anti-Collision Robot 1/14 – 5/14

• Designed (Using LabVIEW) and implemented a robot using low-voltage DC motors, infrared sensors, PIC16F877A microcontroller, and Lithium-ion batteries.

• Developed the code for the microcontroller to receive the signals from the sensors and change the direction of rotation of the motors to turn the robot in the direction away from the obstacle using Embedded C language.

LEADERSHIP EXPERIENCE

IGNIUM, Technical fest 2014 – 2015

• Organized national level technical fest IGNIUM, under Indian Society for Technical Education (ISTE) Students Chapter at G. Narayanamma Institute of Technology and Science, Hyderabad, India.

• Worked with 500 applicants and 60 participants communicating about the details of the fest through e-mail each year. Also, maintained questionnaire panels for the presentations.

AWARDS

• Won I place by presented a paper on ‘Tri-Gate Transistors’ in ELECTERT-2014, a national level technical fest, conducted in Chaitanya Bharathi Institute of Technology, Hyderabad, India.

• Presented a paper on ‘Solar Energy Systems’ in Vignan Institute of Technology, Hyderabad, India in 2015

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