Kalpan Mehta

+1-201-***-**** adeifb@r.postjobfree.com github.com/KSM479

EDUCATION

Master of Science in Computer Engineering New York University GPA - 3.7 / 4 May 2020 Courses:Advanced Hardware Design Computer Systems Architecture VLSI System & Architecture Data Structures & Algorithms Lab Assistant -Hardware Security (Spring 2020) Teaching Assistant - Advanced Hardware Design (Fall 2019) Bachelor of Technology in Electronics and Communication Nirma University GPA - 7.67 / 10 May 2018 Courses: High-Performance VLSI Design Embedded System System Modeling & Design Testing & Verification of Electronic Circuit Publications: 8-bit custom MIPS Microprocessor Electromagnetic Interference Reduction SKILLS

Languages:Verilog, VHDL, C, Python, C++, SystemVerilog, TCL, Embedded C, Perl, Assembly Language Software & Tools:Xilinx Vivado, Synopsys Design Compiler, PrimeTime, MATLAB, ModelSim, KiCAD, Cadence Virtuoso, MATLAB, GIT Hardware & Instruments:Raspberry Pi, Nexys 4 Artix-7 FPGA, Function Generators, Oscilloscopes, Signal Analyzer Protocols & Peripherals:SPI/SSI, I2C, UART, CAN, USB, RS-232, RS-485, PWM, ADC, DAC, Timers, Interrupts, DMA (Basic) WORK EXPERIENCES

Graduate Assistant New York University Sept 2019 - May 2020 Assisted my mentor in optimizing and implementing Post Quantum Cryptography(PQC) Algorithm-CRYSTALS Dilithium on FPGA.

● Optimized the AES module in the PQC algorithm to run in 14 clock cycles by merging the array elements in blocks of 4 and optimizing the loops of the module.

● Redesigned the SHA-256 algorithm in C and verified the functioning of the algorithm before converting it to RTL level design.

● Improved the NTT (Number Theoretic Transform) algorithm by rewriting the loops to save almost 3000 clock cycles at the end.

● Used the Vivado HLS tool to convert the C language implementation of the algorithm into synthesized Verilog Implementation.

● The final result was a 33% decrease in the latency of the PQC algorithm. Currently implementing the algorithm on FPGA Project Assistant Indian Space Research Organization Jan 2018 - May 2018 Responsible for developing a temperature controller to stabilize the Laser diode of the Tunable Diode Laser Absorption Spectrometer.

● Designed and developed a prototype of the PID controller using op-amps, capacitors, and resistors to increase/decrease voltage level based on the temperature change. The temperature was tentatively measured using a thermistor.

● Used the KiCAD tool for schematic capture and PCB layout for the circuit and enhanced it’s EMI and thermal performance. ACADEMIC PROJECTS

FPGA Implementation of AES Crypto Algorithm with UART Xilinx Vivado HLS Verilog, C March 2020 Implemented AES Crypto Algorithm on Nexys 4 FPGA board and verified its functionalities on 10 different test cases.

● Used the Xilinx Vivado HLS tool to create an IP for the AES crypto algorithm from C.

● Integrated the IP with the UART by writing a UART wrapper module in Verilog and implemented the project on the FPGA.

● Wrote a C code to run the algorithm on FPGA for 10 test cases and verified the results for those test cases. ASIC Implementation of Self Disabling BIST module for a 256x4b SRAM Synopsys Design Compiler Verilog December 2019 Designed a self-disabling Built-in Self-Test (BIST) module for an SRAM which was able to verify the correctness of the SRAM using 6 different test patterns. The module was designed in Verilog with a single testbench to validate all 6 test patterns.

● Used the Synopsys design compiler tool to synthesis the design using 32nm libraries.

● Applied timing constraints of 3 ns clock (333 MHz frequency) and fixed the timing violations by adding buffers in PrimeTime tool.

● Performed Static Timing Analysis to remove setup and hold time violations. Imported the design on IC Compiler 2 Tool. Real-Time Image Processing System Raspberry Pi Python October 2019 Developed a Real-Time Digital Processing System using Raspberry Pi that takes input using an infra-red camera and controls the movement of the mechanical arm based on the input. Code was developed in python using OpenCV2 based libraries on the Linux OS.

● The gesture captured by the camera was based on HSV (Hue, Saturation, Value) segmentation. Spaces between fingers were found by finding the largest contour in the mage and then finding convexity defects (where the curve has bulged inside). FPGA Implementation of 32 bit byte-addressable MIPS Based Processor Xilinx Vivado VHDL November 2018 Developed a 32-bit byte-addressable MIPS based processor in VHDL that can execute any instruction in a single clock cycle. Implemented the processor on a Basys-3 FPGA Board over its 7-Segment display, performed RC-5 Cipher with a self-written assembly code loaded to its memory.

● Verified the functioning of the processor using a VHDL testbench which tested the model for 20 test cases.

● Implemented “Debug Mode” for the processor which lets the user single-step through instructions to help track register values. PARTICIPATION

Finalists Hack@ Design Automation Conference, Las Vegas Jan 2019 - June 2019

● Wrote TestBenches in System Verilog and performed the static analysis of RISC V Ariane SoC to detect security vulnerabilities. LEADERSHIP & EXTRACURRICULAR ACTIVITIES

● Completed course “SoC Verification Using SystemVerilog” on Udemy.

● Organizer HackNYU 2020 delivered a healthy and sanitized hackathon for 350 students amidst the COVID-19 outbreak.

● 'Hall of Fame', Renaissance Academy, Ahmedabad for excellent performance in GRE(Q-170 V-155 Total 325/340 ) For further details, please visit – https://kalpanmehta.wixsite.com/portfolio/

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