CHARLES E

KACZOR

** ****** ** *.*. Box ***, Barre, Mass 01005, 508-***-****, adefk6@r.postjobfree.com

PROFESSIONAL SUMMARY

Summary: Lead Electrical Engineer with a BSEE and over 25 years of design, documentation (Doors, Agile), design of circuits and development, including trouble shooting and failure analysis and project management of complex analog and digital products for the medical device and high-tech industries. Hands-on experience designing, developing, evaluating, integrating and testing embedded software, micro-controllers, microprocessors, 10BaseT and 100BaseT Ethernet, PCI(33/66MHz) and PCI-X(33/66/100/133MHz) designs, ATM protocol integrated hardware designs, low and high-powered circuits, power electronics, servo-controllers, VME 64 based architecture and FPGA's. Experience with the following tools: Cadence Concept/HDL, schematic capture, Spectraquest - Signal Integrity Orcad - schematic capture, Viewlogic - schematic capture, ModelSim - FPGA simulation for an FFT based environment (FPGA), Verilog, VHDL/HDL modeling for XILINX FPGA, Digital PLL design (Phase Lock Loop), Spice and PSpice, Allegro - Layout and routing software, LabVIEW, MATLAB, PADS PCB (layout software), SolidWorks, Hyperlynx - signal integrity software, DxDesigner PCB layout and simulation software and Rockwell 17XX(PLC) design experience for manufacturing control. Low noise, high voltage power designs. IEC 60601 experience. Experience with Linux debug. .3D modeling. Experience with the ARM microprocessor as a storage and network director used in a current test environment. Started the introduction of Altium into General Dynamics. This could be used for future designs. Altium is a "next generation" schematics capture and host preparer which has much more power than Cadence or Viewlogic with a simplistic GUI interface. It allows for a robust design with multiple embedded interfaces using both SMT style devices and through hole devices. PIC 16/ PIC 32.ISO 60601 and ISO14644. Xilinx Vivaldo and Simulink.

SKILLS

PCB design

High speed design

High speed simulation

MATLAB

Proficient in CAD

Proficient in Signal Integrity

Analog / Digital design

EXPERIENCE

Sr Electrical Engineer

Benton Dickson via Black-diamond network (consultant)

09/2019 – 1/3/2020

revised and implemented method to determine battery Internal impedance. Used during initial qualification.

Reimplemented proprietary insulin administration device to meet FDA approval and CE mark.

Altium used as cad system during the entire process.

RS485 (differential pair communications) for remote diagnostic devices when patient has attached device.

DMX used to NOT overheat (Thermal characteristics) of the drivers.

Xilinx Vivaldo and Simulink used.

Manufacturing of device moving to Ireland.

Position finished. - Position moving to Ireland.

Sr Electrical Engineer

Medtronic – Littleton Mass February 2019-May 2019

Device analysis debug of battery recharge circuits along with component selections.

Sr Electrical Engineer

Abiomed, Inc American Contractors Inc.

3/13/2017 – Feb 2019

Lifecycle Engineering Completed over 300 SPR (System Problem Reports) and have written/corrective over 300 failure investigations since March of 2017.

This included fixes relative to the operation and design of the Impella Console hardware.

This involved small redesigns, test vehicles and devices to test and repair the Impella Consoles.

Have also included suggestions of what is necessary for device that are end of life replacements.

This included any ECO (engineering change orders) as required.

Involving both the mechanical assembly as well as the hardware fixes., Research and development including Prototyping: All Microsoft office including Microsoft word, Microsoft Excel, Microsoft PowerPoint, Microsoft Visio, and Microsoft Access.

Embedded System Design including: Embedded System Design including troubleshooting to assembly and component level Designed and developed and debugged from concept through schematic entry to Printed Circuit Board (PCB) for new product Digital Acquisition Controller using and using embedded microcontrollers.

Digital and Analog design includes dual 12 bit, 500 MHz front end (500 MHz A/D - Analog Devices A/D), using the Altera Stratix IV (EP4S40G5H402N) FPGA with utilization of 45%.

Additional space was intentionally left within the FPGA for future enhancements.

Multiple 100 MHz clocks were used to supply the FPGA and A/D's on the PCB.

A programmable input clock was used for the A/D to provide 20% skew if needed.

However, this board also included a PIC 133 Processor for remote access, HDMI Interface from the FPGA and Ethernet Interface via the PIC.

Due to board requirements and density, microminiaturization of power was used along with input power developed from +12V source ONLY.

BPCB had its own power (LDO) to minimize noise from the main input power of 3.3v derived off the main input power via the PCIe connector.

This board also is plug compatible with a standard PCIe (1x, 4x, or 8x) interface via the FPGA.

Original design was kept at 12 LAYERS using some creative routing.

The physical dimensions for the PCB board were 9" X 4.1".

The PCB is different than a 2U configuration but well under the 12" maximum for standard PCIe.

This printed circuit board is to be used in a future laser driven product for Endoscopy.

The above design used Altium (Summer 09 and Version 10) as a cad environment for both schematic capture and PCB layout and PCB design.

RS485 (differential pair communications) for remote diagnostic devices when patient has attached device.

DMX used to NOT overheat (Thermal characteristics) of the drivers. Device used MAX487CPA/SN75176BP became over heated unless DMX was implemented

GPU / CPU architecture for new product development.

Schematics were accepted by customer along with Layout and routing.

Once board arrives from vendor, DVT will be started and completed within 1 year for sale of product.

This was mixed signal technology.

Based upon IEC for compliance.

Created VHDL models Schematics - Altium Board Level - Altium SI Board Level - Spectraquest Board Level - LTSpice System Level - eField Created VHDL models, All Microsoft office including Microsoft word, Microsoft Excel, Microsoft PowerPoint, Microsoft Visio, and Microsoft Access.

Embedded System Design including: Embedded System Design including troubleshooting to assembly and component level Design and develop DVT plan for customer Implantable device.

Produced "new etch".

Debugged etch and provided guidance to bring product to market.

Used upon recommendation of customer GSSWISS as the board house to build etch.

Board completed however Cirtec customer stopped project.

Shelved project.

Nothing else in the pipeline.

DVT plan still needs to be executed to be a viable product per FDA requirements.

This was mixed signal technology.

Sr Electrical Engineer

Advanced Instruments Norwood, Ma

3/24/2016 –1/11/2017

New Product purchased from EU.

Does not pass class B, however, does pass class A.

PCB needed many filters to eliminate Radiated frequencies of 100 mhz.

Added logic (filters) on PCB.

Simulated PCB in PSpice.

Trying alternatives.

Contract soon to be completed.

IEC 60601 used for compliance.

Simulated using VHDL prior to submittal as a task.

Sr Electrical Engineer

Nocturnal Industries Worcester, Ma

9/26/2016 – 10/7/2016

0

Taught class on PSPICE and the utilization of OrCAD as the initiator.

Good class but way too short.

Class finished on time and on schedule.

Current engineers were knowledgeable but needed some help to bring it all together.

First week was theory; second week was lab work.

Total attendees = 12 engineers.

Protect Industries via GCR (General Computer Resources) Waltham Ma

7/21/2016 – 9/24/2016

Designed a small (1/3") PCB for switching assembly for new detector.

Two iterations due to mechanicals that changed.

Board is currently being used for prototype.

Designed, placed ready to build Analog POCB which takes small signal analog, converts the signal into a digital form to use on a 40mps (Mega Bits per second) A/D used on a remote PCB.

This included all the power and power sequencing for the PCB.

This will be used in the new product currently under development.

Engineered the new product, did not due the architecture which needs refinement.

Designed a 6" X 6" PCB which would allow testing of the entire system one module at a time.

If changes occur, then this will need to ECO's as it replicates the current system architecture.

GPU / CPU architecture for new product development.

Implemented small XILINX (ZYNQ - 7000) for test board A/D Control circuit.

All power requirements and sequencing have been met.

Tasked to devise small room to handle Class 6 clean room (hair cover, boots, gown and beard cover) (small modular) for radioactive elements and minizine dust particles within the newly renovated building.

This incorporated ISO 14644 as a base and will keep the particulates down within reason for assembly of newly designed devices.

Presented to management and will be added to floor planning of new building renovations.

Reasoning is to minizine particulates as well as isotope Isolation during manufacturing process.

Task completed.

Concluded short DVT (Device Verification Testing) of a new device prior to design.

Original design had many unknowns during build cycle.

The entire power system needed to be all quite power considering a 100 MS (100 mega sample) A/D was used to determine the amount of indirect radiation (photons) were being emitted from the source used.

RS232 (single ended communications) for remote diagnostic devices when lead was detected through the instrument.

Rebuilt power subsystem with all LDO's instead of switching power supplies.

Implemented WIFI as a base.

Created models and simulation for new system using VHDL.

System Level - JTEND Board Level - Spectraquest Board Level - LTSpice VDHL model generation and simulation ISO 14644 Test generation and support for existing product.

Schematics - Altium MATLAB XILINX - ZYNQ 7000.

Sr Electrical Engineer

Protect Industries Waltham, Ma

4/1/2016 – 7/20/2016

Protect Industries

Designed a small (1/3”) PCB for switching assembly for new detector. Two iterations due to mechanicals that changed. Board is currently being used for prototype.

Designed, placed ready to build Analog POCB which takes small signal analog, converts the signal into a digital form to use on a 40mps (Mega Bits per second) A/D used on a remote PCB. This included all the power and power sequencing for the PCB. This will be used in the new product currently under development. Engineered the new product, did not due the architecture which needs refinement.

Designed a 6” X 6” PCB which would allow testing of the entire system one module at a time. If changes occur, then this will need to ECO’s as it replicates the current system architecture. GPU / CPU architecture for new product development. Implemented small XILINX (ZYNQ – 7000) for test board A/D Control circuit. All power requirements and sequencing have been met.

Tasked to devise small room to handle Class 6 clean room (hair cover, boots, gown and beard cover) (small modular) for radioactive elements and minizine dust particles within the newly renovated building. This incorporated ISO 14644 as a base and will keep the particulates down within reason for assembly of newly designed devices. Presented to management and will be added to floor planning of new building renovations. Reasoning is to minizine particulates as well as isotope Isolation during manufacturing process. Task completed.

Sr Electrical Engineer

Curadel, Worcester, Ma

1/24/2016 - 2/24/2016

Meets ISO6061 standard.

Used Spectraquest (PCB simulator for boards) along with LTSpice for SI/EMI.

Since no system diagram available, no system simulation could be done.

GPU / CPU architecture for new product development.

Implemented WIFI for communications.

Power subsystem for PCB was all LDO's to minimize noise.

Based upon IEC 60601 for compliance.

Started VHDL model creation and simulation.

Schematics - OrCAD EMI/RFI - Spectraquest, Board Level System Level - JTEND Board Level - Spectraquest Board Level - LTSpice Test generation and support for existing product VHDL model generation and creation.

Sr Electrical Engineer

Reveal Imaging - a Leidos Company Billerica, Ma

9/2/2014 – 1/22/2016

Research and development including Prototyping: All Microsoft office including Microsoft word, Microsoft Excel, Microsoft PowerPoint, Microsoft Visio, and Microsoft Access.

Foreplaning for the ZYNQ-7000 FPGA to reduce cost and buildability of the controller interface for the CT120.

Most of the design was finished, project was canceled due to other issues.

Schematic (OrCAD) and layout capture using PADS Professional (Xpedition).

Embedded System Design including troubleshooting to assembly and component level and using embedded microcontrollers New and older products.

ARM7 and ARM9 development.

Designed and built from schematics through PCB and prototyping new test system for CT 120.

This is a pure research division of Reveal Imaging.

CT120, this is a CT scanner used in airports as luggage before transport in air with no contraband items including explosives.

New product development for Checkpoint DR.

Found several issues such as noise on PCB related to wrong capacitor being used and adjacent noise in detectors found to be bad grounding in detectors.

Full failure mode analysis of unknown devices along with root cause analysis and validation.

Completed design/software for Raspberry Pi (PIC 9) microprocessor quadrature Counter using a simple stepper motor and written software/driver for the LS7366 chip to show viability and physical count.

This was mixed signal technology. RS485 (differential pair communications) for remote diagnostic devices when patient has attached device. RS485 was chosen due to distances which were required for control.

DMX used to NOT overheat (Thermal characteristics) of the drivers. Device used MAX487CPA/SN75176BP became over heated unless DMX was used. Specifically, for light control and activation.

Implemented small XILINX (ZYNQ - 7000) for test board A/D Control circuit.

DVT on existing products.

DVT (Device Verification Testing) of a new device prior to above design.

GPU / CPU architecture for new product development.

Switching power supplies were sufficient for power.

WFI implemented now for internal communications.

Created models (VHDL) to input into ModelSim.

Schematics - OrCAD, Altium EMI/RFI - Spectraquest, Board Level System Level - JTEND XILINX - ZYNQ 7000 MATLAB Board Level - Spectraquest Board Level - LTSpice WIFI Test generation and support for existing product VHDL models created.

Sr. Electrical Engineer

HeartWare Inc, IGATE contracting firm Framingham, Ma.

4/28/2014 – 8/29/2014

Research and development including Prototyping: All Microsoft office including Microsoft word, Microsoft Excel, Microsoft PowerPoint, Microsoft Visio, and Microsoft Access.

Embedded System Design including troubleshooting to assembly and component level fix CAPA's those were outstanding.

Along with the CAPA's, assigned To Cirtec Medical systems to help aid in several Protocols for release of Many Co's and CR's within the Agile system.

Performed minor designs of the battery and battery interface subsystem.

This included both schematics and included PCB layout and design.

Full failure mode analysis of unknown devices and product testing along with project management.

Based upon IEC 60601 for compliance, Research and development including Prototyping: All Microsoft office including Microsoft word, Microsoft Excel, Microsoft PowerPoint, Microsoft Visio4/28/2014, and Microsoft Access.

Full failure mode analysis of devices.

Embedded System Design including troubleshooting to assembly and component level and using embedded microcontrollers Designed, developed and debugged several PCB's for the GiGaSort Project including one 6 U PCB containing 80 ADC's (Analog to Digital Converters) (embedded system design) with several other functions including control and sequencing to a control PCB.

Each ADC had their own power supply (LDO) to minimize noise at the power level.

The PCB was LVDS to/from the ADC's and LVDS to the output backplane.

(Circuit design) Created and debugged several test PCB's to be used with the GiGaSort Project.

Created and designed several PCB's to be used with the latest Viper Project.

This included a 3Kv front end and control using the PSOc3 CPU test PCB.

Used LabVIEW to incorporate and prove any changes to existing product.

This was an aid to producing simple diagnostics for current product set.

This was mixed signal technology.

Schematic and layout capture using PADS Professional (Xpedition).

Directed to change to Altium by management.

Mentor Graphics was too expensive to maintain and use.

DVT on existing products.

DVT (Device Verification Testing) of a new device prior to above design.

GPU / CPU architecture for new product development.

Based upon IEC 60601 for compliance.

Created VHDL models.

Schematics - Altium Board Level - Altium SI Board Level - Spectraquest Board Level - LTSpice System Level - eField Test generation and support for existing product VHDL models created.

Sr Electrical Engineer

CytonomeST Boston, Mass

4/01/2012 – 4/11/2014

.

Embedded System Design including troubleshooting to assembly and component level and using embedded microcontrollers Designed, developed and debugged several PCB's for the GiGaSort Project including one 6 U PCB containing 80 ADC's (Analog to Digital Converters) (embedded system design) with several other functions including control and sequencing to a control PCB. Each ADC had their own power supply (LDO) to minimize noise at the power level.

Sr Electrical Engineer

Nine Point Medical Cambridge, Mass

12/2011 – 4/2012

Designed and developed and debugged from concept through schematic entry to Printed Circuit Board (PCB) for new product Digital Acquisition Controller using and using embedded microcontrollers

. Digital and Analog design includes dual 12 bit, 500 MHz front end (500 MHz A/D – Analog Devices A/D), using the Altera Stratix IV (EP4S40G5H402N) FPGA with utilization of 45%. Additional space was intentionally left within the FPGA for future enhancements.

Sr Electrical Engineer

Cirtec Medical Systems East Longmeadow, Mass

9/14/11-12/19/11

Design and develop DVT plan for customer Implantable device. Produced “new etch”. Debugged etch and provided guidance to bring product to market. Used upon recommendation of customer GSSWISS as the board house to build etch. Board completed however Cirtec customer stopped project. Shelved project. Nothing else in the pipeline. DVT plan still needs to be executed to be a viable product per FDA requirements. This was mixed signal technology.

Principle Electrical Engineer

The Charles Stark Draper Laboratory, Inc, Massachusetts Institute of Technology / General Dynamics Cambridge, MA

7/2/05 – 9/14/11

February 2005 - April 2012

Research and development including Prototyping at Draper Labs working for General Dynamics: Embedded System Design including troubleshooting to assembly and component level While at General Dynamics in Pittsfield Mass and Draper Laboratory in Cambridge lead a team for DFT (Design for Test) for a current Trident Missile Life Extension Program (MK6LE).

This involved design for test and design for manufacturing (DFT and DVM).

This not only required a security clearance which I currently hold but also design and test of necessary hardware and software.

JTAG was a major contributor in this area because of board densities and space.

The central microprocessor used is the MC68000 micro (Motorola MC68000 family) along with its supporting hardware.

Both Draper and General Dynamics have taken the approach of using JTAG as a central point for test accessibility.

Currently Cornelis is the vendor of choice even though many others exist.

Using JTAG in a pure digital environment such as with a microprocessor speeds time to market and efficiency when boards are being tested.

On the other hand, Analog is best tested using determination of both Voh/Vol by current available test methods.

This guarantees that correct levels are met, and correct power can be achieved.

Also, used the ARM9 microprocessor as an interface creating a new "storage" environment and a new IP domain to send externally data from the test environment monitored constantly by operators external to the test areas.

Used Doors as a tracking-based system for future and present issues/developments.

GPU / CPU architecture for new product development for high speed sensor development (Triple port VRAM) Working with the current safety organization for "checks" against all known safety issues.

This was and is a major undertaking for what is known as LCS or the Littoral Combat ship.

While at General Dynamics AIS, DVT/DMT was achieved due through debug, simulation, and signal Integrity of the common processor board which uses the Motorola 6800 microprocessor as a base.

The board has high complexity as it not only contains the Micro Controller for the Motorola 6800 microprocessor but also has a 16-bit A/D for system monitoring functions.

Most functions were checked/Tested through JTAG.

The board speed was set at 100 MHz however the testing initially was performed at 5 MHz due to limitations of JTAG.

Official board test "at speed" was performed when the board was inserted into system.

No TEST points were added as required by the customer and all testing was accomplished from the edge connector to the internal board/module.

This board/module also uses a controlling ASIC (Commonly called the RSUP or controller ASIC) developed initially through XILIX technology and when it was determined to work functionally per documentation, it was transitioned to a pure ASIC.

This however was not a "burned ASIC" as all simulation was performed on the West Coast.

Testing was highly successful using the implementation of JTAG which shortened the development time of the board/module.

Schematic and layout capture using PADS Professional (Xpedition).

Started the introduction of Altium into General Dynamics in accordance with current policies.

Maybe used in future designs.

Started VHDL modeling.

Achieved Six Sigma.

Electrical Engineer

Walker Magnetics Worcester, Ma.

1/1/05-4/1/2005

Designer of new product line involving high power electronics used in the manufacturing industry for chuck controls, scrap magnets and their high-power controls.

Sr. Design Engineer

Sky Computers Inc Chelmsford, Massachusetts

1/01 –7/04

This was mixed signal technology.

Embedded System Design including troubleshooting to assembly and component level All Microsoft office including Microsoft word, Microsoft Excel, Microsoft PowerPoint, Microsoft Visio, and Microsoft Access.

Led the design and development of 3 generations of high-speed Multi-switches using the Multichannel InfiniBand Mellanox high-speed switches.

Product to be used in visual recognition system provided.

Coordinated the efforts of PCB and component vendors, Quality Engineering and Design to ensure that Multi-switches were being developed on time and on budget Responsible for design of analog high-speed buses, analog power electronics, digital microprocessor, embedded firmware, micro-controllers and FPGA development.

Switching out rates were 3.14 GHz.

The first generation was a 6U processor Since time was of the essence, used PADS PCB to design and route several small PCB's used in debug and test for all boards.

This included test fixtures for 6U, 2U and 3U designs.

Led the development of a 2U processor card using the Motorola G4 (7447 and 7457) processor in combination with the Gallileo Discovery memory controller chip using standard SDRAM technology.

combination with the Galileo Discovery II memory controller chip, utilizing DRR2100 for performance reasons.

Incorporated the first entrance of the HCA chip from Mellanox.

HCA represents Host Channel Adapter.

Utilized a 20 Layer PCB using buried capacitance to reduce ground bounce and signal cross talk.

The 3U Processor was a true SMP system board in that two processors on the single board were used to "share" memory during operation.

Designed embedded firmware for Xilinx FPGA's for use in the 2U and 3U Blade Servers Performed analysis to ensure Signal Integrity and minimize crosstalk.

Used PSpice to guarantee high speed memory interface (DDR - Discover II) and was forced to reduce memory bandwidth due to out of tolerance condition within the memory controller.

Downgraded performance of central memory interface from true DDR 266 (133 MHz) to 125 to guarantee margin.

GPU / CPU architecture for new product development.

Published a paper regarding ground bounce and pinning selection in connector fields.

Lead engineer responsible for overseeing the efforts of 3 designers and engineers Designed the 100BaseT interconnect which controlled and communicated with other boards "within the box".

This was the central communications channel from board to board within the entire product set which contained either a 10 or 12 board solution.

Dual processor boards had a 10-board limit requirement "within the box" due to thermal requirements.

Design of "off board" PCI-X, 133MHz, with a fall back to 66 MHz (jumper selectable not software controllable) Customer requirement dictated the fall back feature be jumper and not under software control.

This design followed a mixed signal design technique in that is was "top down".

Each portion of the design was simulated separately then included to build the eventual system.

This is a time consuming and compute intensive way however it becomes very effective with excellent results.

Debug of all internal interfaces at both the assembly level and at the higher system level using emulation at its lowest point and C++ at the driver level.

Aided in driver debug for the blade server.

Design Tools Used: Cadence Concept/HDL - schematic capture, Spectraquest - Signal Integrity, Orcad - schematic capture, Viewlogic - schematic capture, ModelSim - FPGA simulation, PSpice.

Schematic and layout capture using PADS Professional (Xpedition).

Directed to change to Allegro by management.

Mentor Graphics was too expensive to maintain and use.

Schematics - OrCAD Layout - PADS then Allegro EMI Board Level - PSpice EMI System Level - eField.

Sr. Design Engineer

Mercury Computer Inc Chelmsford, Massachusetts

4/98 – 1/01

Embedded System Design including troubleshooting to assembly and component level.

Led the design, documentation and development of the Vantage RT PCI based MC750 processor card used in the medical field by G.E.

Medical systems for diagnostic digital X-Ray, including both digital processing and analog power circuits.

Provided accurate documentation to ensure compliance with FDA standards The Vantage RT board is the image processing board of digital X-Ray as produced by GE today.

Designed the back-plane adapter cards to daisy chain up to 16 multilevel switches.

Designed a motion-positioning sensor for the Vantage RT Digital X-Ray Unit Designed an 18-processor switch card (9U form factor) which had VME 64 architecture as a base.

This same design was carried over to another multiprocessor product called Jetstream.

The base design used the Tundra Universe II as a bridge between the VME 64 bus and the internal PCI bus used on the designed board.

Schematic and layout capture using PADS Professional (Xpedition).

Directed to change to Allegro by management.

Mentor Graphics was too expensive to maintain and use.

Design Tools Used: Spectraquest - Signal Integrity, Viewlogic - schematic capture Schematics - Viewlogic (OrCAD) EMI Board Level - PSpice EMI System Level - eField.

Design Engineer/Sr. Design Engineer/Integration Engineer

Digital Equipment Corporation Marlboro, Massachusetts

12/80 – 6/98

Held several positions over 18 years focused on electrical design, test and integration Final position prior to division being sold to Cabletron was as an integration engineer.

Was responsible for seeking, validating and integrating partner technology to incorporate into telecommunications switch programs.

GPU / CPU architecture for new product development.

Also, responsible for design and debug of all devices which failed using anything available for debug from RTOS to VMS to Tops-20(36 Bit mainframes).

Designs included: Memory Upgrades 36-bit main frames Computer Interconnect Clusters for which 6 US patents and 1 Canadian patent were received.

ATM hub way switch using OC3 and OC12 technologies Design Tools Used: Viewlogic - schematic capture, CAE2000 - Techtronic's entry version of schematic capture, Spice and many others Schematics - Viewlogic(OrCAD) Many years (approximately 10 years) involved in modeling using HDL/VHDL to be input through to final chip/device.

Field Service Technician

January 1974 - January 1980

RTL

for Prime Computer and GE Medical Systems.

EDUCATION

BSEE

Central NE College of Technology

January 1985

Worcester Jr. College ASEE

January 1974

ACCOMPLISHMENTS

3/1993 Canadian Patent #1,315,412, Computer Interconnect Coupler for clusters of Data Processing Devices

10/1992 United States Patent #5,199,611, Data Integrity in Computer Interconnecting Devices 9/92 United States Patent #5,138,611, Computer Fail Safe Transmission of Computer Interconnects

10/1992 United States Patent #5,108981,611, Data Integrity in Computer I Devices

9/92 United States Patent #5,138,611, Computer Fail Safe Transmission of Computer Interconnects

8/1992 United States Patent #5,139,611, Blocking Message Transmission or Signaling Error in Response to Message

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