Assistant Project

OBJECTIVE

To work for an organization which provides me the opportunity to enhance my skills and knowledge and to work for the growth of the organization

ACADEMIC QUALIFICATIONS

Year Degree/Certificate School/University CGPA

2016-till now B-Tech (ECE) Rajiv Gandhi University of Knowledge Technologies 8.53 2016

Pre University Course (PUC)

Rajiv Gandhi University of Knowledge Technologies 9.1 2014 SSC (State Board)

Z.P.H.S 9.8

TECHNICAL SKILLS

● Hardware Description Language : Verilog

● Programming Languages : C,Basic Java, Python

● Operating Systems : Windows,Zorin,Ubuntu

● EDA Tools : Xilinx Vivado Tool

● Software Packages :Multisim, Matlab

RESEARCH PROJECTS

B-Tech(E-4) Ongoing Project: Implementation of Area efficient and high throughput Multiple Input and Multiple Output systems using Distributed Arithmetic on FPGA. Team size : 04

Duration : Sep 2019 to till now

Usable Technologies : Programming in Verilog and Vivado tool Project Supervisor: Mr. Shyam Perika Designation:Assistant Professor Department:E.C.E Description : MIMO systems are used to increase the data rates.MIMO consists of multiple transmitters and receivers.These are mainly used in communication purpose.Here we implementing this MIMO using DA to decrease the hardware.Here we are using a 4x4 channel matrix to implement a MIMO system. B-Tech(E-3) MINI Project:EXPLORING FPGA

Team size : 04

Duration : June 22 to July 15 in 2019

Usable Technologies : Programming in Verilog and Vivado tool Project Supervisor: Mr. Shyam Perika Designation:Assistant Professor Department:E.C.E Description : This project is designing a digital clock.It is designed in 24 hour time format. The format of the time is hh:mm:ss.We done audio interfacing on fpga.Displaying a colour image on fpga using vga interface. It is designed in xilinx vivado tool by using verilog language.

B-Tech Intern Project: FPGA IMPLEMENTATION OF ADAPTIVE FILTER USING OFFSET BINARY CODING USING VERILOG AND MATLAB

Team size : 04

Duration :June 10th 2019 to june 20th 2019

Usable Technologies: programming in verilog, Matlab and vivado tool Project Supervisor: Mr. Shyam Perika Designation: Assistant Professor Department: E.C.E Description : The objective of this paper is about designing an adaptive filter to increase the throughput. They used OBC to increase the speed. The output is verified by both verilog and matlab and its hardware implementations on FPGA. B-Tech(E-3) MINI Project:ADAPTIVE FILTER USING DISTRIBUTED ARITHMETIC USING VERILOG AND MATLAB Team size : 04

Duration : 03 Months (Jan 2019 to April 2019)

Usable Technologies: programming in verilog, Matlab and vivado tool Project Supervisor: Mr. Shyam Perika Designation: Assistant Professor Department: E.C.E Description : The objective of this paper is about designing an adaptive filter by decreasing the hardware and increasing the throughput. Hardware is decreased by replacing the multiplier with DA. It consists of two LUT 's.Those are F-LUT and A-LUT for filter weights and input sample updation respectively. The two LUT’s are updated in parallel which results in increasing the throughput.It is done in both matlab and verilog languages. B-Tech(E-3) MINI Project:ADAPTIVE FILTER USING VERILOG AND MATLAB Team size : 05

Duration : 03 Months (oct 2018 to dec 2018)

Usable Technologies : programming in verilog, Matlab and vivado tool Project Supervisor: Mr. Shyam Perika Designation: Assistant Professor Department: E.C.E Description : Adaptive filter is a digital filter which is used in Digital Signal Processors like echo cancellation,system identification and in many application. It is a linear filter and it updates it filter weights by using adaptive algorithms. We used LMS algorithm to design it. We designed it in both verilog and matlab languages. B-Tech(E-3) MINI Project:RECURSIVE OFFSET BINARY CODING(OBC) IMPLEMENTATION ON FPGA USING VERILOG Team size : 02

Duration : 07 Days (november 2018)

Usable Technologies : Verilog

Project Supervisor: Mr. Shyam Perika Designation: Assistant Professor Department: E.C.E Description : ROBC is used for calculating the inner product like OBC and DA.It is very fast because here the ROM size is decreased by four times.It uses more hardware because additional gates are used for generating the ROM address.It is designed in verilog and its hardware implementations on FPGA. B-Tech(E-3) MINI Project:OFFSET BINARY CODING(OBC) IMPLEMENTATION ON FPGA USING VERILOG Team size : 02

Duration : 15days (october 2018)

Usable Technologies : Verilog

Project Supervisor: Mr. Shyam Perika Designation: Assistant Professor Department: E.C.E Description : OBC is also a technique to calculate the inner product.DA is bit serial in nature and it is a slow.It stores the precalculated values in a LUT.Here ROM size is decreased by 2 for fast calculations.By using the OBC we can increase the speed but hardware is increased due to other logic gates.It is designed in verilog and its hardware implementations on FPGA.

B-Tech(E-3) MINI Project:DISTRIBUTED ARITHMETIC (DA) IMPLEMENTATION ON FPGA USING VERILOG Team size : 02

Duration : 01 Month (september 2018 to october 2018) Usable Technologies : Verilog

Project Supervisor: Mr. Shyam Perika Designation: Assistant Professor Department: E.C.E Description :DA is an efficient technique for calculation of inner product or multiply and accumulate (MAC).It takes more area,for calculating inner product by using multipliers.We can implement this MAC operation with ROM look up table(LUT). The precalculated values are stored in the LUT.DA uses adders and shifters to perform MAC operation which takes low area.It is designed in verilog and its hardware implementation on FPGA. B. Tech(E-3) MINI Project:DIGITAL CALENDAR USING VERILOG Team size : 01

Duration : 02 Days in november 2018

Usable Technologies : Verilog

Project Supervisor: Mr. Shyam Perika Designation: Assistant Professor Department:E.C.E Description : This project is designing of a calendar. It is designed only for a specific year which means it displays the dates,months and days of a year which we are specifying. It is designed in verilog language in xilinx vivado tool. B-Tech(E-2) MINI Project: CONVERSION OF ROLL NUMBERS TO ID NUMBERS Using Digital Electronics in Multisim

Team size : 02

Duration : 01 Months (July 2016 to August 2016)

Usable Technologies s: Multisim

Project Supervisor: Mr. Shyam Perika Designation: Assistant Professor Department: E.C.E Description : This project is about the conversion of the student roll numbers in a class into their respective ID numbers. This is designed by using the decoders. This project is related to digital electronics. We implemented this design in multisim software.

PUC (P2) Project:ATLAS

Team size : 06

Duration : 05 Months (December 2015 to April 2016) Project Supervisor : Sk.SaleemBabu (Mentor in English) Description : The main objective of this project is creating an earthly environment in space for living organisms. So we designed a space settlement named atlas for living. In this space settlement we have to generate all the necessary things for living example oxygen,food,gravity etc.. and we have to reuse the wastage of humans. AREAS OF INTERESTS

● Digital Logic Design

● Programming

● Digital VLSI

● VLSI Designing and Testing

EXTRA and CO-CURRICULAR ACTIVITIES

● Worked as a volunteer for counseling in RGUKT,NUZVID in the year 2015-2016.

● Served as a NSS candidate for two years.

PERSONAL INFORMATION

● Address for Correspondence:Mamidibattula Sireesha, D/O Srinivasa Rao,Temburu village,Pathapatnam mandal,Srikakulam district,Andhra Pradesh,India, Pin:532201 SCHOLASTIC ACHIEVEMENTS

● Selected for Space Settlement Design contest conducted by NASA Ames Research Center in 2016

● Secured first place in Intramural Cultural Competitions conducted by RGUKT in 2016

● Participated in Technical Fest 2k17 conducted by Vikas Group of Institutions.

● Participated in TECHZITE-2k15 conducted by RGUKT in 2015.

● Secured first place in Tennikoit game conducted by Inter Schools Athletic Association in 2011 DECLARATION

I hereby declare that the above information is true to the best of my knowledge. Date: 19-11-2019 Signature

Place: Nuzvid M.Sireesha

Contact this candidate