Engineer Software

ASHRAF JAVEED

Mobile: +91-990-***-**** E-Mail: ******.******.**@*****.***

Skype: Please Provide LinkedIn: www.linkedin.com/in/ashrafjaveed/

Currently in Bengaluru, India; willing to relocate at the earliest

SENIOR SYSTEM SOFTWARE ENGINEER

Firmware Applications Development System Configuration Diagnostics Tools Development

Highly-skilled and result-driven professional with 20+ years of experience in managing and performing firmware design & validation with Expert in PCIe Gen3, Gen4 enabling in Intel SoC, chipset components like USB, SMBus, SPI, and power management support using ACPI methods. Experienced in creating test plans for RTL validation, defining, and running system simulation models. Proven track record delivering quality software in a fast-paced, dynamic environment consisting of a culturally diverse set of people. Good understanding of product development life cycle and Software Engineering Process. Familiar with Agile methodology and Waterfall Model. Excellent management skills; demonstrated proficiency in leading and mentoring individuals to maximum levels of productivity while forming a cohesive team environment.

TECHNICAL ACUMEN

Programming/Scripting Languages

C, C++, Microsoft x86 Assembly Language (ASM), Python, .BAT

Firmware for PC Systems

BIOS Functional programming, UEFI Standard programming

Legacy PC Systems

x86 Architecture, Real Mode 32-bit Protected/Flat mode, x64 mode, x86 Assembly-level language instruction set, MMX, SSE & SSE2, PCI legacy & MMCFG H/W access programming

Utility Programming

EFI based embedded debug tool, diagnostic tool for CPU and GUI, DOS

Windows Programming

Visual C++ 6, Win32 APIs, WINSOCK for IPC, Multi-thread programming & synchronizing objects programming, Win PE programming

Source Control Tool

Microsoft Visual SourceSafe, IBM Rational Clear Case, Dimension, Tortoise SVN, Perforce, Git

Debugging Tool

Intel’s ITP, AMD’s HDT, Microsoft’s Visual Studio 6 integrated Debugger, DOS’s DEBUG & DEBUG32 tool, USB Analyzer

Documentation Tool

MS Word. MS PowerPoint, MS Excel, MS Visio, MS MPP, Adobe Acrobat

IDE's

Eclipse, UltraEdit, Notepad++, Slick Edit, Microsoft Visual Studio 6, AMI’s VeB

EXPERIENCE

Intel Technologies Private Limited, Bengaluru, India Feb 2008 - Ongoing

Software Engineer Since Jan 2017

Silicon IP Architecture and Infrastructure Development in Silicon Firmware Engineering Group

Publishing register description of Compute Express Link (CXL) in the UEFI Open Source MDE package industry-standard header files

Working with platform architecture workgroup to define new system firmware flow for Hot-Plug functionality of CXL (Compute Express Link) device as an accelerator, and memory device

Defining new EFI protocol for PCI Express by driving UEFI Platform Initialization (PI) specification change, in order to support the device-specific platform policies in the platform firmware

Enhancing UEFI kernel PCI bus driver to initialize 10 PCIe features across all the PCIe hierarchy in a system

UEFI Silicon enabling Firmware for Intel Highspeed IO PCIe Gen4, and system firmware for Intel Xeon-D products

Collaborated with an IIO UEFI workgroup remotely at 3 different Intel site teams

Designed and delivered silicon enabling firmware drivers for the Intel's first PCIe Gen4 subsystem in Xeon

Leveraged experience in delta feature review and filed firmware change requirements, and readiness for pre-silicon validation environments

Attained the launch readiness qualification for the 2nd generation Xeon D family

Provided resolution for the SDLC clearance, directed a team of 2 for code changes and its qualification to achieve the launch milestone

BIOS Engineer Apr 2016 - Dec 2016

Silicon enabling UEFI Firmware for Intel Premium/Atom-based SoC Processors

Designed and developed IA32 Firmware modules for Intel's System-on-a-Chip (SoC) family processor's south cluster IP components

Carried out design/validation teams for new feature addition, silicon workarounds inclusion, BIOS readiness for Power-on and validation phase

Led the virtual PCH IAFW workgroup of 4 to support the chip power-on and platform functional validation phases

Optimized IAFW design to seamlessly support both discrete and integrated connectivity solutions

UEFI Firmware Engineer Mar 2013 - Mar 2016

Silicon enabling UEFI Firmware for Intel Xeon Processor D-15xx, E3-12xx V4 Server family

Carried out technical scoping, feature designing, collaborative development and the delivery of integrated UEFI-based firmware/BIOS for Intel Xeon processor 14nm 1st gen family of Microserver (D) SoC

Regulated BIOS issues, interlock with stakeholders, Silicon design/validation terms

Led the BIOS engineer team and closely coordinated with Silicon Design/Architecture team during Pre-Silicon phase for BIOS readiness and new Silicon feature implementation

Steered review meetings with Silicon Design/Validation teams, comprehend the change list in BIOS, for both Pre-silicon and Post-silicon development

Achievements

Bagged Intel Division Recognition Award (DRA) [Oct - Dec 2015] for role modeling ownership and collaboration to support A-step PRQ targeted program; enabled a hybrid emulation model of new generation Intel Xeon Processor D SKU, booting BIOS and Intel validation OS in task-force mode

Received Intel Division Recognition Award (DRA) [Apr - Jun 2014] for:

oOutstanding Silicon validation and enabling results in emulation for finding 100+ Silicon design bugs during the pre-silicon phase, before Power-on ensuring Silicon design health and post-silicon readiness

oPreserving Intel Xeon Processor D-15xx committed revenue and post-silicon validation plan by holding the Intel Xeon Processor D-15xx schedule through the first-ever initialization of BIOS and validation of a CPU with non-functioning cores

Senior Validation Engineer - BIOS Feb 2008 - Mar 2013

Silicon Validation BIOS ownership of Intel's Server Integrated IO (IIO) component

Delivered IIO driver stack for the Intel Xeon E7 x8xx family processor for EX segment, in the EDK II code base, from Pre-silicon phase till product launch

Architected IIO BIOS driver stack setup in UEFI firmware codebase as per the Intel EDK II specification standard

Coordinated with cross-validation teams to define any Silicon workarounds in BIOS for VT-d, IOxAPIC, Crystal Beach 3.2 DMA, PCIe Gen3 training, power, performance-related settings

Server Silicon Validation BIOS support for Intel Proprietary validation environments

Designed and developed BIOS for CPU validation environment, for power-on, volume validation environments

Provided specialized BIOS for CPU Silicon Validation environments

Involved in debugging, implementation of validation hooks, and BIOS porting

Represented the team in software process improvement board and process owner/chairperson for the local team's software practice process planning and implementation

Achievement

Submitted a paper titled 'Automated Validation System for CPUSV BIOS' at Intel Design and Test Technology Conference 2011

Dell Corporation, Bengaluru, India Apr 2007 - Feb 2008

PG Software Development Advisor

Worked on legacy BIOS development for PowerEdge T605 server

Owned block releases of BIOS subsystem, for server products, like PowerEdge 2970, PowerEdge 6950, and PowerEdge SC1435

American Megatrends, Inc. (AMI), Norcross, GA, USA Jun 2000 - Apr 2007

Senior Software Engineer

Submitted 7 US patent applications assigned to American Megatrends Inc. (approved by US Patent and Trademark Office)

Introduced USB 2.0 debug port interface in driver stack for AMI firmware debug solutions

Recognized for providing extensive cross-platform support for BIOS Configuration tools

Leveraged expertise in below-mentioned products

oSoftware Debugger Tool as a Development utility for legacy BIOS and EFI 32/x64

oAMI Graphical Setup Environment (GSE) for AMI Tiano’s firmware (EFI)

oAMI Pre-Boot Applications (PBA)

oBIOS Configuration Tools

oSoftware Diagnostic Tools

Co-inventor for the following patents assigned:

'Updating a Firmware Image Using a Firmware Debugger Application', US Patent #8407526, Mar 26, 2013

'Updating a Firmware Image Using a Firmware Debugger Application', US Patent #8135993, Mar 13, 2012

'Power-on Self-test Data Notification', US Patent #8078856, Dec 13, 2011

'System and Method for Debugging a Target Computer using SMBUS', US Patent #8010843, Aug 30, 2011

'Updating a firmware image using a firmware debugger application', US Patent #7861119, Dec 28, 2010

'System Management interrupt interface wrapper', US Patent #7827339, Nov 2, 2010

'Method for testing memory in a computer system utilizing a CPU with either 32-bit or 36-bit memory addressing', US Patent #7293207, Nov 6, 2007

ACADEMICS & ACCREDITATION

Bachelor of Engineering - Computer Science and Engineering, Bangalore University, India (1998)

Professional Membership

Member of PCI-SIG Website (pci-sig.com)

Member of UEFI.org and GitHub/Tianocore

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