Design Engineer Project
Resume:
C M GAYATHIRI DEVI
****************@*****.***
linkedin.com/in/gayathiri-devi-2118ba9a
OBJECTIVE
Seeking a challenging career opportunity in RTL Design and Integration in a cutting edge technology in a reputable organization to expand my knowledge and skills. WORKING EXPERIENCE
Joined as a RTL design trainee from June 2019 to December 2019 in FLDEC Systems Private Systems Limited, Chennai.
Working as RTL Design Engineer from January 2020 to Present in FLDEC Systems Private Systems Limited, Chennai.
PROFILE
Good understanding of ASIC and FPGA design flow.
Knowledge in Digital design and Verilog.
Good knowledge in CDC, Linting.
Basic Knowledge in Synthesis.
Knowledge of Perl and TCL scripting.
EDA TOOLS
SKILLS SUMMARY
HDL Verilog
Simulators Spyglass, Questasim
Protocols I2C, SPI, VGA, UART, ARP, UDP, AXI and PTP Design suite FPGA and ASIC
Synthesis, Lint & CDC Design Compiler, Spyglass CDC and Spyglass Lint Scripting TCL and Perl
MS office tools MS-WORD, MS-EXCEL, MS-PowerPoint
EDUCATIONAL QUALIFICATION
Degree/School Board/University Year of passing CGPA/Percentage M.Tech [VLSI Design] VIT University-
Vellore
2019 8.11
B.E.[Electronics and
Communication Engg.]
GTEC-Vellore 2015 8.06
HSC Sunbeam MHSS
Vellore
2011 82.33%
S.S.L.C Sunbeam MHSS
Vellore
2009 79.2%
PROJECT DETAILS
Project: 1 Implementation of IEEE 1588 protocol for IEEE 802.11 WLAN Contribution: • Configuration of Marvell 88E1111 Ethernet PHY chips in DE2115 board with 1G Ethernet transceiver.
• Implemented making FPGA as one device and PC as another device and tried to synchronise timing between them Description The synchronisation is done as two phases: Phase I establishes master- slave hierarchy and Phase II synchronises clock using event and general messages.
PTP is used to precisely synchronise computers over a line.UDP is used as a transport layer protocol.
Tools Altera Quartus-II, Wireshark packet analyser and Questasim Project: 2 Bi – Synchronous FIFO for communication between two clock domains on SoCs
Description Implemented Bi-synchronous FIFO schematic using Cadence Virtuoso. This technique is used to communicate between two IP’s of different clock frequencies.
Tools Cadence Virtuoso
Project: 3 ASIC Implementation of High Efficiency Video Coding 2D Approximate DCT
Description Performed recursive sparse matrix decomposition and by making use of the symmetries of DCT basis vectors for deriving the proposed approximation algorithm.The speed is increased in the proposed design with the fully parallel approach and the proposed area efficient fully parallel DA architecture for 2D-DCT are realized.
Tools Verilog, Synopsys DC compiler
Project: 4 CORDIC based FFT Architecture
Description The twiddle factors used in FFT is generated by CORDIC algorithm for efficient usage of memory and easy access.A 512 point FFT architecture is going to be implemented using CORDIC algorithm. Simulations are going to be made by MATLAB.
Tools MATLAB, Verilog, Synopsys DC compiler.
Project: 5 FPGA based speed DC controller of motor using PWM technique Description Designed the PWM Controller in order to control the speed of a DC motor drive using FPGA as a digital controller.
Tools Altera Quartus-II, Questasim
Project: 6 Pulse triggered flip-flop design using clock gating and pull-up scheme
Description Objective is to implement power efficient pulsed-triggered flip-flop with clock-gating and pull-up control scheme. By applying an XOR- based clock-gating scheme, the low power efficiency is achieved in the proposed design.
Tools Cadence Virtuoso
COURSES
• Trained in RTL Integration and Design course
• Completed Online course on VLSI Design Methodologies by Maven silicon on July 2018.
• Actively participated in IEEE International Conference on Microelectronic Devices,Circuits and Systems(ICMDCS’17) on “I/O Interface design-challenges and trends in the industry”,organized by the Department of Micro & Nanoelectronics,SENSE,VIT University,Vellore, held on 10th August,2017.
• Actively participated in IEEE International Conference on Microelectronic Devices,Circuits and Systems(ICMDCS’17) on “Low Power Verification” organized by the Department of Micro & Nanoelectronics,SENSE,VIT University,Vellore held on 20th August,2017. DECLARATION
I hereby declare the veracity of the information furnished above. Place: Vellore (C M GAYATHIRI DEVI)
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