Engineer Design

GALESHWAR JORIGA

Call: +91-807*******

E-mail: **************@*****.***

Present Address:

Marathahalli,.

Bangalore -560037,

Karnataka.

Permanent Address:

H No: 8-120/2,

Damaracherla Village,

Damaracherla Mandal,

Nalgonda(Dist),

Telangana–508311.

Credentials:

• Have good knowledge in C and

basics of oops concepts.

• Knowledge in High level Register

Transfer Level (RTL) language such

as VerilogHDL.

• Hands on experience Verilog and

SystemVerilog on Simulation and

synthesis tool.

• Possess strong verification skills like

random and advertisings testing as

well as debugging.

• In-depth knowledge of debug tools,

logic design concepts and simulators

like Xilinx and VCS simulator.

• Good understanding of Synthesis,

Static Timing Analysis (STA) using

DC compiler Synopsys.

• Ability to write tcl script for setup

files in DC compiler.

• Good knowledge on Computer

Architecture.

• Good at problem solving and

Working under Pressure.

*CAREER OBJECTIVE

Looking for an opportunity where there is a chance to share and upgrade my knowledge for the organization to be served. To improve employ ability and to play key role in the development of the organization.

* EDUCATION

Master Of Technology (VLSI SYSTEM DESIGN) – 2013-16 JNT-UNIVERISITY (SEER AKADEMI) – 76.3%, JNTU, ANANTHAPUR. Bachelor of Technology (E.C.E.) – 2008 - 2012

SREE DATTHA INSTITUTIONS – 71.15%, JNTU, HYDERABAD. Intermediate (MPC) – 2006 - 2008

NALANDA JUNIOR COLLEGE – 86.80%

BOARD OF INTERMEDIATE EDUCATION.

SSC (10th Standard) – 2006

NAGARJUNA HIGH SCHOOL – 77.50%

BOARD OF SECONDARY EDUCATION.

* TECHNICAL SKILLS

Programming Languages : C, VerilogHDL.

VLSI EDA Tools : Gplcver,

Synopsys(VCS Simulator, DC Compiler)

Cadence (NCSim).

HVL : System Verilog.

Operating Systems : Linux, Windows.

Scripting : Perl, Basics Python.

*SUMMARY

MODULES WORKED ON :

Digital designs and FSM( melay and moore )

Worked on different projects from design to verification Good understanding of the ASIC flow and Digital Design. Having 1 YEAR hands on Practical Experience on RTL coding with Verilog HDL Using Synopsys EDA Tool.

*PROFESSIONAL EXPERIENCE (0-6)

• Worked as Internship Trainee engineer from December - 2014 to 2015 May in SAANKHYA LABS PVT.LTD.

*JOB PROFILE

• Verified IIR Filter by using the File I/O Test bench.

• Develop the test cases to verify IIR Filter.

• Debugged the test failure and interaction with the design team.

• Developed the Reference model for IIR filter in C and VerilogHDL.

*PROFESSIONAL EXPERIENCE (1 yr 2 months)

• Worked as Project Developer engineer from 2018 October to 2019 December in INSPIRE IT LABS.

*JOB PROFILE

• Design the RTLHDL code for IEEE Projects.

• Verified the function of the designs using system verilog.

• Conducting the seminars and teaches the Digital design.

• Debugged the test failure and interaction with the design team. PROJECTS WORKED:

1. FSM Design and FIFO

2. ALU and Memory module RAM

3. Low area multiplexer using Cordic

4. I2C and SPI Protocols

Role: Design and Verification.

HDL & HVL: Verilog HDL & System Verilog.

EDA Tools: Synopsys (VCS Simulator, DC compiler), Cadence (NC simulator). 1. Understanding the Specification.

2. Preparation of Verification Plan.

3. Preparation of Test cases.

4. Developed the Reference model in C language.

5. TB coding and debugging simulation failures.

6. Code and Functional Coverage.

7. Line and Toggle coverage

8. Create a Make file for compilation.

9. Understand the mapped and unmapped Net list of RTL Design.

*PROFESSIONAL EXPERIENCE (1 yr 6months)

• Worked as Assistant Professor from 2016 December to 2018 June in CMR inst of Technology.

*JOB PROFILE

• Deals Advance Digital Electronics and Microprocessor Lab

• Deals M.tech and B.tech Projects

• Deals Logic Synthesis Lab using DC compiler

• Worked as CRT Trainer

* EXTRACURRICULAR ACTIVITIES

• Participated in ARM processors work shop conducted by Central Gov. ATIEPI.

• Participated in VLSI design workshop conducted by Central Gov. IETE.

• Served as Captain for ECE department Kabaddi Team in Graduation.

• Organized the Cultural event for ECE Subhiksha in our college.

• Solving Rubik’s cube and Writing songs.

* PERSONAL INFORMATION

Father's Name : Srinivasa Rao

Gender : Male.

Nationality : Indian.

Marital Status : Single.

Languages : English, Hindi, Telugu.

* DECLARATION

I hereby declare that the information furnished above is true to the best of my Information knowledge belief.

Place :

Date : (J. Galeshwar)

Contact this candidate